Switch control circuit and electronic device using the same

1. A switch control circuit, configured for coupling a baseboard management controller (BMC) to a backplane chip, comprising:

a switch circuit coupled between the BMC and the backplane chip; and

a logic component coupled between the BMC and the switch circuit to obtain a logic control signal from the BMC, and configured to output a switch signal to the switch circuit to turn on or off the switch circuit according to the logic control signal outputted by the BMC;

wherein the switch circuit is configured to control a connection between the BMC and the backplane chip according to the switch signal outputted by the logic component; and

wherein the switch circuit comprises a first electronic switch; the first electronic switch comprises a first electronic switch first terminal, a first electronic switch second terminal, and a first electronic switch third terminal; and the first electronic switch first terminal is electrically coupled to a BMC clock pin, the first electronic switch second terminal is electrically coupled to a backplane chip clock pin, the first electronic switch third terminal is electrically coupled to the logic component.

2. The switch control circuit of claim 1 , wherein the logic component comprises a logic component first input terminal, a logic component second input terminal, a logic component ground terminal, a logic component power supply terminal, and a logic component output terminal; the BMC comprises a BMC first general purpose input output (GPIO) and a BMC second GPIO; and the logic component first input terminal is electrically coupled to the BMC first GPIO, the logic component second input terminal is electrically coupled to the BMC second, the logic component ground terminal is grounded, the logic component power supply terminal is electrically coupled to a power supply, and the logic component output terminal is electrically coupled to the switch circuit.

3. The switch control circuit claim 2 , wherein the switch circuit further comprises a capacitor, a first resistor, a second resistor, and a third resistor; the first electronic switch first terminal is electrically coupled to the power supply through the first resistor, the first electronic switch second terminal is electrically coupled to the power supply through the second resistor, the first electronic switch third terminal is electrically coupled to the logic component output terminal through third resistor, and the first electronic switch third terminal is electrically coupled to ground through the third resistor and the capacitor.

4. The switch control circuit of claim 3 , wherein the switch circuit further comprises a second electronic switch, a fourth resistor, a fifth resistor, and a sixth resistor; the second electronic switch comprises a second electronic switch first terminal, a second electronic switch second terminal, and a second electronic switch third terminal; and the second electronic switch first terminal is electrically coupled to a BMC data pin, the second electronic switch first terminal is electrically coupled to the power supply through the fourth resistor, the second electronic switch second terminal is electrically coupled to a backplane chip data pin, the second electronic switch second terminal is electrically coupled to the power supply through the fifth resistor, the second electronic switch third terminal is electrically coupled to the logic component output terminal through sixth resistor, and the second electronic switch third terminal is electrically coupled to ground through the sixth resistor and the capacitor.

5. The switch control circuit of claim 4 , wherein the first electronic switch is a field effect transistor (FET), the first electronic switch first terminal is a FET source, the first electronic switch second terminal is a FET drain, and the first electronic switch third terminal is a FET gate.

6. The switch control circuit of claim 5 , wherein the second electronic switch is a FET, the second electronic switch first terminal is a FET source, the second electronic switch second terminal is a FET drain, and the second electronic switch third terminal is a FET gate.

7. The switch control circuit of claim 6 , wherein when the BMC is required to communicate with the backplane chip, both the BMC first GPIO and the BMC second GPIO outputs the logic control signal at the low-voltage level to the logic component first input terminal and the logic component second input terminal, the logic component outputs a switch signal at the high-voltage level to turn on the first electronic switch and the second electronic switch, and the BMC communicates with the backplane chip normally.

8. The switch control circuit of claim 1 , wherein the logic component is a nor gate.

9. A electronic device comprising:

a baseboard management controller (BMC);

a backplane chip; and

a switch control circuit coupled between the baseboard management controller (BMC) and the backplane chip and comprising:

a switch circuit configured for coupling between the electronic device BMC and the device backplane chip; and

a logic component coupled between the BMC and the switch circuit to obtain a logic control signal from the BMC, and configured to output a switch signal to the switch circuit to turn on or off the switch circuit according to the logic control signal outputted by the BMC;

wherein the switch circuit is configured to control a connection between the BMC and the backplane chip according to the switch signal outputted by the logic component; and

wherein the switch circuit comprises a first electronic switch; the first electronic switch comprises a first electronic switch first terminal, a first electronic switch second terminal, and a first electronic switch third terminal; and the first electronic switch first terminal is electrically coupled to a BMC clock pin, the first electronic switch second terminal is electrically coupled to a backplane chip clock pin, the first electronic switch third terminal is electrically coupled to the logic component.

10. The electronic device claim 9 , wherein the switch circuit further comprises a capacitor, a first resistor, a second resistor, and a third resistor; the first electronic switch first terminal is electrically coupled to the power supply through the first resistor, the first electronic switch second terminal is electrically coupled to the power supply through the second resistor, the first electronic switch third terminal is electrically coupled to the logic component output terminal through third resistor, and the first electronic switch third terminal is electrically coupled to ground through the third resistor and the capacitor.

11. The electronic device of claim 10 , wherein the switch circuit further comprises a second electronic switch, a fourth resistor, a fifth resistor, and a sixth resistor; the second electronic switch comprises a second electronic switch first terminal, a second electronic switch second terminal, and a second electronic switch third terminal; and the second electronic switch first terminal is electrically coupled to a BMC data pin, the second electronic switch first terminal is electrically coupled to the power supply through the fourth resistor, the second electronic switch second terminal is electrically coupled to a backplane chip data pin, the second electronic switch second terminal is electrically coupled to the power supply through the fifth resistor, the second electronic switch third terminal is electrically coupled to the logic component output terminal through sixth resistor, and the second electronic switch third terminal is electrically coupled to ground through the sixth resistor and the capacitor.

12. The electronic device of claim 11 , wherein the first electronic switch is a field effect transistor (FET), the first electronic switch first terminal is a FET source, the first electronic switch second terminal is a FET drain, and the first electronic switch third terminal is a FET gate; and the second electronic switch is a FET, the second electronic switch first terminal is a FET source, the second electronic switch second terminal is a FET drain, and the second electronic switch third terminal is a FET gate.

13. The electronic device of claim 12 , wherein when the BMC is need to communicate with the backplane chip, both the BMC first GPIO and the BMC second GPIO outputs the logic control signal at the low-voltage level to the logic component first input terminal and the logic component second input terminal, the logic component outputs a switch signal at the high-voltage level to turn on the first electronic switch and the second electronic switch, and the BMC communicates with the backplane chip normally.