Semiconductor device
View Patent ↗A semiconductor device includes a plurality of nonvolatile memory cells ( 1 ). Each of the nonvolatile memory cells comprises a MOS type first transistor section ( 3 ) used for information storage, and a MOS type second transistor section ( 4 ) which selects the first transistor section. The second transistor section has a bit line electrode ( 16 ) connected to a bit line, and a control gate electrode ( 18 ) connected to a control gate control line. The first transistor section has a source line electrode ( 10 ) connected to a source line, a memory gate electrode ( 14 ) connected to a memory gate control line, and a charge storage region ( 11 ) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc<tm.
1. A flash memory module comprising:
a first driver circuit including a plurality of first drivers, and selecting one of the first drivers;
a second driver circuit coupled to the first driver circuit and including a plurality of second drivers, the second driver circuit selecting one of the second drivers based on an output state of the selected first driver; and
a writing control circuit which latches read data based on the selected first driver and the selected second driver upon a write operation, and which selects the latched data upon a read operation.
2. A flash memory module according to claim 1 , wherein
the first driver circuit selects among the plurality of the first drivers based on a first address signal.
3. A flash memory module according to claim 2 , further comprising:
a memory array including a global bit line and a control gate line,
wherein an output of the selected first driver is coupled to the second driver circuit via the control gate line.
4. A flash memory module according to claim 3 , wherein
the writing control circuit is connected to the global bit line, and latches the read data read from the global bit line.
5. A flash memory module according to claim 3 , wherein
the writing control circuit latches write control information supplied to the global bit line upon a write operation, and selects the latched data based on a second address signal upon a read operation.
6. A flash memory module according to claim 5 , wherein
the first address signal and the second address signal are supplied from an address bus via an address buffer.