Memory controller utilizing an error coding dispersal function
View Patent ↗A computing core includes memory and a memory controller. The memory is partitioned into a user section and a kernel section. The user section is divided into a first set of pillars and the kernel section is divided into a second set of pillars. The memory controller is operable to dispersed storage error encode a data segment of user data into a set of encoded user data slices. The memory controller is further operable to store the set of encoded user data slices in the first set of pillars of the user section. The memory controller is further operable to dispersed storage error encode a data segment of system data into a set of encoded system data slices. The memory controller is further operable to store the set of encoded system data slices in the second set of pillars of the kernel section.
1. A computing core comprises:
memory that is partitioned into a user section and a kernel section, wherein the user section is divided into a first set of pillars that is based on a first dispersed storage network (DSN) memory set within a DSN, wherein the kernel section is divided into a second set of pillars that is based on a second DSN memory set within the DSN; and
a memory controller operably coupled to the memory, wherein the memory controller is operably to:
dispersed storage error encode a first data segment of user data into a set of encoded user data slices;
store the set of encoded user data slices in the first set of pillars that is based on the first DSN memory set within the DSN of the user section;
dispersed storage error encode a second data segment of system data into a set of encoded system data slices; and
store the set of encoded system data slices in the second set of pillars that is based on the second DSN memory set within the DSN of the kernel section.
2. The computing core of claim 1 , wherein the memory comprises one or more of:
a main memory; and
an interface coupling to one or more of a hard disk drive, an external FLASH memory, and an external dispersed storage network (DSN) memory.
3. The computing core of claim 1 , wherein the memory controller is further operable to:
retrieve a decode threshold number of encoded user data slices of the set of encoded user data slices from the memory;
dispersed storage error decode the decode threshold number of encoded user data slices to recover the first data segment of the user data as a recovered data segment and provide the recovered data segment to a processing module of the computing core.
4. The computing core of claim 1 , wherein the memory controller is further operable to:
retrieve a decode threshold number of encoded system data slices of the set of encoded system data slices from the memory;
dispersed storage error decode the decode threshold number of encoded system data slices to recover the second data segment of the system data as a recovered data segment; and
provide the recovered data segment to processing module of the computing core.
5. The computing core of claim 1 further comprises:
the user section is logically divided into the first set of pillars; and
the kernel section is logically divided into the second set of pillars.
6. The computing core of claim 1 further comprises:
the user section is physically divided into the first set of pillars; and
the kernel section is physically divided into the second set of pillars.
7. The computing core of claim 1 further comprises:
the system data including one or more of: an operating system and an application program interface (API); and
the user data including one or more of: a user application and a software driver.