Semiconductor device, manufacturing method of the same, and electronic device
A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.
1. A method for manufacturing a semiconductor device, comprising the steps of:
depositing a first insulating layer over a substrate;
depositing a first oxide insulating layer over the first insulating layer;
depositing a first oxide semiconductor layer over the first oxide insulating layer;
forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with a first mask;
depositing a third oxide insulating layer over the second oxide semiconductor layer and the first insulating layer;
depositing a second insulating layer over the third oxide insulating layer;
depositing a first conductive layer over the second insulating layer;
forming a gate electrode layer and a gate insulating layer by etching the first conductive layer and the second insulating layer with a second mask;
depositing a third insulating layer over the gate electrode layer, the second oxide semiconductor layer, and the first insulating layer;
forming a sidewall insulating layer comprising a region in contact with a side surface of the gate electrode layer by performing dry etching on the third insulating layer;
depositing a second conductive layer over the gate electrode layer, the sidewall insulating layer, the second oxide semiconductor layer, and the first insulating layer;
depositing a third conductive layer over the second conductive layer; and
forming a low-resistance region in the second oxide semiconductor layer by performing heat treatment,
wherein the second conductive layer comprises a first element,
wherein the third conductive layer comprises a second element,
wherein the second oxide semiconductor layer comprises a third element, and
wherein the low-resistance region comprises the first element, the second element and the third element.
2. The method for manufacturing the semiconductor device according to claim 1 ,
wherein the first element is any one of cobalt, nickel, platinum, vanadium, chromium, and palladium, and
wherein the second element is any one of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, rhodium, iridium, and cobalt.
3. The method for manufacturing the semiconductor device according to claim 1 , wherein the low-resistance region comprises a region comprising an alloy.
4. The method for manufacturing the semiconductor device according to claim 1 , wherein the heat treatment is performed at a temperature higher than or equal to 450° C. and lower than or equal to 650° C.
5. A method for manufacturing a semiconductor device, comprising the steps of:
depositing a first insulating layer over a substrate;
depositing a first oxide insulating layer over the first insulating layer;
depositing a first oxide semiconductor layer over the first oxide insulating layer;
forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with a first mask;
depositing a third oxide insulating layer over the second oxide semiconductor layer and the first insulating layer;
depositing a second insulating layer over the third oxide insulating layer;
forming a third insulating layer by performing planarization treatment on the second oxide insulating layer;
forming a fourth insulating layer with a groove portion that reaches the third oxide insulating layer by etching part of the third insulating layer with a second mask;
depositing a fifth insulating layer over the fourth insulating layer and the third oxide insulating layer;
depositing a first conductive layer over the fifth insulating layer;
forming a gate electrode layer and a sixth insulating layer by performing planarization treatment on the first conductive layer and the fifth insulating layer until the fourth insulating layer is exposed;
forming a gate insulating layer by etching the fourth insulating layer and the sixth insulating layer with the gate electrode layer as a mask;
depositing a seventh insulating layer over the gate electrode layer, the second oxide semiconductor layer, and the first insulating layer;
forming a sidewall insulating layer comprising a region in contact with a side surface of the gate electrode layer by performing dry etching on the seventh insulating layer;
depositing a second conductive layer over the gate electrode layer, the sidewall insulating layer, the second oxide semiconductor layer, and the first insulating layer;
depositing a third conductive layer over the second conductive layer; and
forming a low-resistance region in the second oxide semiconductor layer by performing heat treatment,
wherein the second conductive layer comprises a first element,
wherein the third conductive layer comprises a second element,
wherein the second oxide semiconductor layer comprises a third element, and
wherein the low-resistance region comprises the first element, the second element and the third element.
6. The method for manufacturing the semiconductor device according to claim 5 ,
wherein the first element is any one of cobalt, nickel, platinum, vanadium, chromium, and palladium, and
wherein the second element is any one of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, rhodium, iridium, and cobalt.
7. The method for manufacturing the semiconductor device according to claim 5 , wherein the low-resistance region comprises a region comprising an alloy.
8. The method for manufacturing the semiconductor device according to claim 5 , wherein the heat treatment is performed at a temperature higher than or equal to 450° C. and lower than or equal to 650° C.
9. A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor layer over a substrate;
forming a gate electrode layer and a gate insulating layer over the oxide semiconductor layer;
forming a sidewall insulating layer comprising a region in contact with a side surface of the gate electrode layer;
depositing a first conductive layer over the gate electrode layer, the sidewall insulating layer, and the oxide semiconductor layer;
depositing a second conductive layer over the first conductive layer; and
forming a low-resistance region in the oxide semiconductor layer by performing heat treatment,
wherein the first conductive layer comprises a first element,
wherein the second conductive layer comprises a second element,
wherein the oxide semiconductor layer comprises a third element, and
wherein the low-resistance region comprises the first element, the second element and the third element.
10. The method for manufacturing the semiconductor device according to claim 9 ,
wherein the first element is any one of cobalt, nickel, platinum, vanadium, chromium, and palladium, and
wherein the second element is any one of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, rhodium, iridium, and cobalt.
11. The method for manufacturing the semiconductor device according to claim 9 , wherein the low-resistance region comprises a region comprising an alloy.
12. The method for manufacturing the semiconductor device according to claim 9 , wherein the heat treatment is performed at a temperature higher than or equal to 450° C. and lower than or equal to 650° C.