IP Library Granted Patent US 10,170,528
Granted Patent B2
US 10,170,528 · App. 15/225,166 · Granted Jan 1, 2019

Display panel and manufacturing method thereof

Inventor: Hideaki Kuwabara (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/3267G02F1/1368G02F1/13306G02F1/133514G02F1/133553G02F1/134309H01L27/1274H01L29/42392H01L29/78621H01L29/78633H01L29/78648H01L29/78672H01L29/78696G02F1/1337G02F1/133345G02F1/133512G02F2001/133342G02F2201/123G02F2201/44G02F2202/104G02F2203/02H01L2251/533
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Quick Facts
Patent No.
US 10,170,528
App. No.
15/225,166
Granted
Jan 1, 2019
Kind
B2
Abstract

Provided is a novel display panel that is highly convenient or reliable. The display device has two display modes: a reflective display mode and a light-emitting display mode. In the light-emitting display mode, light display is performed by transmitting light from a light-emitting element overlapping with an opening in a pixel electrode of a reflective display element. A switching element of the reflective display element and a switching element electrically connected to the light-emitting element are formed over one substrate. They are each a transistor whose channel formation region is formed in a silicon-containing film, specifically a polysilicon film.

Claims (65)

1. A display panel comprising:

a driver circuit;

a signal line electrically connected to the driver circuit; and

a pixel electrically connected to the signal line, the pixel comprising:

a first display element comprising a first conductive film;

a second conductive film comprising a region overlapping with the first conductive film;

an insulating film comprising a region between the first conductive film and the second conductive film;

a pixel circuit electrically connected to the second conductive film and the signal line, the pixel circuit comprising a first transistor comprising silicon in a channel formation region; and

a second display element electrically connected to the pixel circuit,

wherein the insulating film comprises a first opening,

wherein the first conductive film comprises a second opening,

wherein the second opening overlaps the second display element, and

wherein the second conductive film is electrically connected to the first conductive film in the first opening.

2. The display panel according to claim 1 ,

wherein the first conductive film is a reflective film and is configured to control an intensity of reflected light,

wherein the reflective film is configured to reflect incident light, and

wherein the second display element is configured to emit light toward the second opening.

3. The display panel according to claim 1 , wherein the first transistor comprises a low-concentration impurity region.

4. The display panel according to claim 1 ,

wherein the driver circuit comprises a second transistor,

wherein the second transistor comprises a first insulating layer over a third conductive film, a semiconductor layer comprising silicon and including the channel formation region over the first insulating layer, a second insulating layer over the semiconductor layer, and a fourth conductive film over the second insulating layer,

wherein the fourth conductive film covers a side surface of the semiconductor layer with the second insulating layer provided therebetween, and

wherein the semiconductor layer is surrounded by the third conductive film and the fourth conductive film in a cross section in a channel width direction.

5. The display panel according to claim 1 , wherein the first transistor comprises polycrystalline silicon.

6. The display panel according to claim 1 , wherein the first transistor is a p-channel type.

7. The display panel according to claim 4 ,

wherein the third conductive film is a first gate electrode of the second transistor, and

wherein the fourth conductive film is a second gate electrode of the second transistor.

8. A display panel comprising:

a driver circuit;

a signal line electrically connected to the driver circuit; and

a pixel electrically connected to the signal line, the pixel comprising:

a first display element comprising a first conductive film;

a second conductive film comprising a region overlapping with the first conductive film;

an insulating film comprising a region between the first conductive film and the second conductive film;

a pixel circuit electrically connected to the second conductive film and the signal line, the pixel circuit comprising a first transistor comprising silicon in a channel formation region; and

a second display element electrically connected to the pixel circuit,

wherein the insulating film comprises a first opening,

wherein the first conductive film comprises a second opening,

wherein the second opening overlaps the second display element,

wherein the second conductive film is electrically connected to the first conductive film in the first opening,

wherein the first display element comprises a charged particle, and

wherein the second display element comprises a layer including a light-emitting material.

9. The display panel according to claim 8 ,

wherein the first display element further comprises a color filter,

wherein the first conductive film is a reflective film configured to reflect incident light,

wherein the second opening overlaps with a structure body, and

wherein the second opening and the structure body are configured to transmit light emitted from the second display element.

10. The display panel according to claim 8 ,

wherein the first conductive film is a reflective film,

wherein the charged particle is a colored charged particle,

wherein the reflective film is configured to reflect incident light,

wherein the second opening overlaps with a structure body, and

wherein the second opening and the structure body are configured to transmit light emitted from the second display element.

11. The display panel according to claim 8 , wherein the first transistor comprises a low-concentration impurity region.

12. The display panel according to claim 8 ,

wherein the driver circuit comprises a second transistor,

wherein the second transistor comprises a first insulating layer over a third conductive film, a semiconductor layer comprising silicon and including the channel formation region over the first insulating layer, a second insulating layer over the semiconductor layer, and a fourth conductive film over the second insulating layer,

wherein the fourth conductive film covers a side surface of the semiconductor layer with the second insulating layer provided therebetween, and

wherein the semiconductor layer is surrounded by the third conductive film and the fourth conductive film in a cross section in a channel width direction.

13. The display panel according to claim 8 , wherein the first transistor comprises polycrystalline silicon.

14. The display panel according to claim 8 , wherein the first transistor is a p-channel type.

15. The display panel according to claim 12 ,

wherein the third conductive film is a first gate electrode of the second transistor, and

wherein the fourth conductive film is a second gate electrode of the second transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2016
From: KUWABARA, HIDEAKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 039307/0251 →
Priority Claims (1)
JP 2015-157620 · Aug 7, 2015 · national
Continuity (1)
Related Publication 20170040403A1 · Feb 9, 2017