IP Library Granted Patent US 10,432,174
Granted Patent B2
US 10,432,174 · App. 15/225,706 · Granted Oct 1, 2019

Closed loop feedback control of integrated circuits

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Quick Facts
Patent No.
US 10,432,174
App. No.
15/225,706
Granted
Oct 1, 2019
Kind
B2
Abstract

Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.

Claims (42)

1. A method, comprising:

adjusting a body bias voltage applied to a body of an integrated circuit to cause a measured value of an operating indicator of the integrated circuit to approach a desired value of the operating indicator;

wherein the body is electrically isolated from one or more electrical components disposed within the body.

2. The method of claim 1 , wherein at least one of the one or more electrical components comprises a transistor.

3. The method of claim 1 , wherein the integrated circuit comprises a microprocessor.

4. The method of claim 3 , wherein the operating indicator comprises a ring oscillator.

5. The method of claim 4 , further comprising counting cycles of the ring oscillator.

6. An integrated circuit comprising:

circuitry configured to adjust a controllable input to the integrated circuit to cause a measured value of a characteristic of the integrated circuit to approach a desired value of the characteristic;

wherein the controllable input includes a body bias voltage applied to a body of the integrated circuit; and

wherein the body is electrically isolated from one or more electrical components disposed within the body.

7. The integrated circuit of claim 6 , wherein the controllable input further comprises an operating voltage of the integrated circuit.

8. The integrated circuit of claim 6 , wherein the controllable input further comprises an operating frequency control input.

9. The integrated circuit of claim 6 , wherein the characteristic corresponds to a gate delay of the integrated circuit.

10. The integrated circuit of claim 9 , wherein the characteristic corresponds to a leakage current of the integrated circuit.

11. The integrated circuit of claim 4 , wherein the characteristic corresponds to only one type of device from the set of P-FETs and N-FETs.

12. An article of manufacture including a computer readable medium having instructions stored thereon that, if executed by a computing device, cause the computing device to perform operations comprising:

adjusting a controllable input of an integrated circuit to cause a measured value of an operating indicator of the integrated circuit to approach a desired value of the operating indicator;

wherein the controllable input includes a body bias voltage applied to a body of the integrated circuit; and

wherein the body is configured to have a bias relative to one or more electrical components disposed within the body.

13. The article of manufacture of claim 12 , wherein the integrated circuit comprises the computing device.

14. The article of manufacture of claim 12 , wherein the controllable input further comprises an operating voltage of the integrated circuit.

15. The article of manufacture of claim 12 , wherein the operating indicator comprises a ring oscillator.

16. The article of manufacture of claim 12 , wherein the operating indicator indicates a behavior of only n-type MOSFETs.

17. A method, comprising:

adjusting a controllable input of an integrated circuit to cause a measured value of an operating indicator of the integrated circuit to approach a desired value of the operating indicator;

wherein the operating indicator comprises a ring oscillator.

18. An integrated circuit, comprising:

circuitry configured to adjust a controllable input to the integrated circuit to cause a measured value of a characteristic of the integrated circuit to approach a desired value of the characteristic;

wherein the controllable input includes a body bias voltage applied to a body of the integrated circuit;

wherein the body is electrically isolated from a source terminal of a field effect transistor in the body; and

wherein the characteristic corresponds to a gate delay of the integrated circuit.

19. An integrated circuit, comprising:

circuitry configured to adjust a controllable input to the integrated circuit to cause a measured value of a characteristic of the integrated circuit to approach a desired value of the characteristic;

wherein the controllable input includes a body bias voltage applied to a body of the integrated circuit;

wherein the body is electrically isolated from a source terminal of a field effect transistor in the body; and

wherein the characteristic corresponds to a leakage current of the integrated circuit.

20. An integrated circuit, comprising:

circuitry configured to adjust a controllable input to the integrated circuit to cause a measured value of a characteristic of the integrated circuit to approach a desired value of the characteristic;

wherein the controllable input includes a body bias voltage applied to a body of the integrated circuit;

wherein the body is electrically isolated from a source terminal of a field effect transistor in the body; and

wherein the characteristic corresponds to only one type of device from the set of P-FETs and N-FETs.

Assignments (9)
CHANGE OF NAME Recorded Mar 4, 2022
From: FACEBOOK, INC.
To: META PLATFORMS, INC.
Reel/Frame 059320/0484 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 058996 FRAME: 0831. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 25, 2022
From: TRANSMETA CORPORATION
To: TRANSMETA LLC
Reel/Frame 059248/0043 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2022
From: TRANSMETA CORPORATION
To: TRANSMETA LLC
Reel/Frame 058996/0831 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2022
From: KONIARIS, KLEANTHES G.; BURR, JAMES B.
To: TRANSMETA CORPORATION
Reel/Frame 058996/0799 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2019
From: INTELLECTUAL VENTURES ASSETS 88 LLC
To: FACEBOOK, INC.
Reel/Frame 048136/0179 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2018
From: INTELLECTUAL VENTURES HOLDING 81 LLC
To: INTELLECTUAL VENTURES ASSETS 88 LLC
Reel/Frame 047014/0629 →
CORRECTIVE ASSIGNMENT TO CORRECT THE STATE IN ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 044097 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded May 25, 2018
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 046245/0753 →
MERGER Recorded Nov 10, 2017
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 044097/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2017
From: TRANSMETA LLC
To: INTELLECTUAL VENTURE FUNDING LLC
Reel/Frame 044037/0039 →