IP Library Granted Patent US 10,176,023
Granted Patent B2
US 10,176,023 · App. 15/227,901 · Granted Jan 8, 2019

Task dispatcher for block storage devices

Inventor: Philip Andrew White (Renton, WA)
Assignee: SCALE COMPUTING, INC.
G06F9/54
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Quick Facts
Patent No.
US 10,176,023
App. No.
15/227,901
Granted
Jan 8, 2019
Kind
B2
Abstract

A system, method, and computer program product are provided for implementing a protocol stack for handling memory access requests associated with one or more block devices. The method includes the steps of allocating a thread to process a task associated with a memory access request for a block device; and executing the thread to process the task, wherein the thread implements a state machine that manages calls to two or more layers of the protocol stack. A task dispatcher is implemented for managing the execution of tasks using at least one thread pool, the tasks managing the calls to the various layers of the protocol stack. The protocol stack may implement abstraction layers for virtual storage devices as well as the real block devices.

Claims (39)

1. A method comprising:

allocating a thread, executed by a processor included in a node, to process a task according to a protocol stack for handling memory access requests associated with one or more block devices included in the node;

executing the thread to process the task, wherein the thread implements a state machine that manages calls to two or more layers of the protocol stack; and

allocating a second thread, executed by the processor, to manage the allocation of a thread pool for processing a plurality of tasks associated with a plurality of memory access requests, wherein the second thread is configured to stall the thread processing the task when a direction of the task changes.

2. The method of claim 1 , wherein the processor is multi-threaded and two or more threads are executed by the processor simultaneously.

3. The method of claim 2 , further comprising:

allocating a third thread to process a second task according to the protocol stack; and

executing the third thread to process the second task,

wherein the thread is included in a first thread pool allocated to tasks having a first priority and the third thread is included in a second thread pool allocated to tasks having a second priority that is higher than the first priority.

4. The method of claim 1 , wherein the protocol stack includes a first layer that implements a server for communicating with one or more clients that generate memory access requests for the one or more block devices.

5. The method of claim 4 , wherein the protocol stack includes a second layer associated with one or more virtual storage device objects, and wherein each memory access request includes an address in a virtual storage device address space.

6. The method of claim 5 , wherein the protocol stack includes a third layer associated with one or more real storage device objects corresponding to the one or more block devices.

7. The method of claim 1 , wherein the task is pushed onto a first task lane in a plurality of task lanes.

8. The method of claim 7 , wherein the task is stalled based on a barrier instruction associated with the first task lane.

9. The method of claim 7 , wherein the plurality of task lanes are included in a task lane hierarchy, and wherein a barrier instruction associated with a parent task lane may stall any task associated with a child task lane corresponding to the parent task lane.

10. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:

allocating a thread, executed by a processor included in a node, to process a task according to a protocol stack for handling memory access requests associated with one or more block devices included in the node;

executing the thread to process the task, wherein the thread implements a state machine that manages calls to two or more layers of the protocol stack; and

allocating a second thread, executed by the processor, to manage the allocation of a thread pool for processing a plurality of tasks associated with a plurality of memory access requests, wherein the second thread is configured to stall the thread processing the task when a direction of the task changes.

11. The computer-readable storage medium of claim 10 , the steps further comprising:

allocating a third thread to process a second task according to the protocol stack; and

executing the third thread to process the second task,

wherein the thread is included in a first thread pool allocated to tasks having a first priority and the third thread is included in a second thread pool allocated to tasks having a second priority that is higher than the first priority.

12. The computer-readable storage medium of claim 10 , wherein the protocol stack includes:

a first layer that implements a server for communicating with one or more clients that generate memory access requests for the one or more block devices;

a second layer associated with one or more virtual storage device objects, wherein each memory access request includes an address in a virtual storage device address space; and

a third layer associated with one or more real storage device objects corresponding to the one or more block devices.

13. A system comprising:

one or more block devices;

a memory that includes a protocol stack for handling memory access requests associated with the one or more block devices; and

a processor coupled to the memory and configured to:

allocate a thread to process a task according to the protocol stack,

execute the thread to process the task, wherein the thread implements a state machine that manages calls to two or more layers of the protocol stack, and

allocate a second thread, executed by the processor, to manage the allocation of a thread pool for processing a plurality of tasks associated with a plurality of memory access requests, wherein the second thread is configured to stall the thread processing the task when a direction of the task changes.

14. The system of claim 13 , the steps further comprising:

allocating a second thread to process a second task according to the protocol stack; and

executing the second thread to process the second task,

wherein the thread is included in a first thread pool allocated to tasks having a first priority and the second thread is included in a second thread pool allocated to tasks having a second priority that is higher than the first priority.

15. The system of claim 13 , wherein the one or more block devices, the memory, and the processor are included in a first node, the system further comprising a second node, wherein a processor in the second node generates a memory access request associated with the task.

Assignments (16)
SECURITY INTEREST Recorded Jan 29, 2026
From: SCALE COMPUTING, LLC
To: TORONTO DOMINION (TEXAS) LLC
Reel/Frame 073633/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2025
From: SCALE COMPUTING, LLC
To: SCALE COMPUTING, INC.
Reel/Frame 072864/0595 →
CHANGE OF NAME Recorded Aug 28, 2025
From: ACUMERA SCALE, LLC
To: SCALE COMPUTING, LLC
Reel/Frame 072699/0326 →
MERGER Recorded Aug 15, 2025
From: SCALE COMPUTING, INC.
To: ACUMERA SCALE, LLC
Reel/Frame 072034/0883 →
RELEASE OF SECURITY INTEREST Recorded Jul 31, 2025
From: BANC OF CALIFORNIA (FORMERLY KNOWN AS PACIFIC WESTERN BANK)
To: SCALE COMPUTING, INC.
Reel/Frame 071898/0667 →
RELEASE OF SECURITY INTEREST Recorded Jul 31, 2025
From: MS PRIVATE CREDIT ADMINISTRATIVE SERVICES LLC AS AGENT
To: SCALE COMPUTING, INC.
Reel/Frame 071901/0365 →
SECURITY INTEREST Recorded Oct 13, 2023
From: SCALE COMPUTING, INC.
To: PACIFIC WESTERN BANK
Reel/Frame 065213/0109 →
RELEASE OF SECURITY INTEREST Recorded Feb 6, 2023
From: AVENUE VENTURE OPPORTUNITIES FUND, L.P.
To: SCALE COMPUTING, INC.
Reel/Frame 062603/0565 →
SECURITY INTEREST Recorded Feb 3, 2023
From: SCALE COMPUTING, INC.
To: NORTH HAVEN EXPANSION CREDIT II LP
Reel/Frame 062586/0059 →
RELEASE OF SECURITY INTEREST Recorded Dec 11, 2020
From: RUNWAY GROWTH CREDIT FUND INC.
To: SCALE COMPUTING, INC.
Reel/Frame 054619/0802 →
SECURITY INTEREST Recorded Dec 11, 2020
From: SCALE COMPUTING, INC.
To: AVENUE VENTURE OPPORTUNITIES FUND, L.P.
Reel/Frame 054619/0825 →
RELEASE OF SECURITY INTEREST Recorded Dec 10, 2020
From: RUNWAY GROWTH CREDIT FUND INC., AS AGENT
To: SCALE COMPUTING, INC.
Reel/Frame 054611/0589 →
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: BET ASSOCIATES III, LLC
To: SCALE COMPUTING, INC.
Reel/Frame 048746/0597 →
SECURITY INTEREST Recorded Mar 29, 2019
From: SCALE COMPUTING, INC.
To: RUNWAY GROWTH CREDIT FUND INC.
Reel/Frame 048745/0653 →
SECURITY INTEREST Recorded Jun 27, 2018
From: SCALE COMPUTING, INC.
To: BET ASSOCIATES III, LLC
Reel/Frame 046212/0831 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2016
From: WHITE, PHILIP ANDREW
To: SCALE COMPUTING, INC.
Reel/Frame 039341/0716 →
Continuity (1)
Related Publication 20180039521A1 · Feb 8, 2018