IP Library Granted Patent US 10,146,963
Granted Patent B2
US 10,146,963 · App. 15/228,738 · Granted Dec 4, 2018

Systems and methods for dynamic external input/output port screening

Inventors: Timothy M. Lambert (Austin, TX); Mukund P. Khatri (Austin, TX)
Assignee: Dell Products L.P.
G06F21/85G06F13/4282
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Quick Facts
Patent No.
US 10,146,963
App. No.
15/228,738
Granted
Dec 4, 2018
Kind
B2
Abstract

In accordance with embodiments of the present disclosure, an information handling system may include a host system comprising a processor, one or more external input/output (I/O) ports, a chipset communicatively coupled to the processor and including an I/O port controller, the I/O port controller interfacing between the processor and the one or more external I/O ports, and a management controller communicatively coupled to the processor configured to provide out-of-band management of the information handling system, and further configured to communicate a port security policy to a component of the chipset such that the I/O port controller dynamically enables and disables, independent of an operating state of the host system, individual ones of the one or more external I/O ports in accordance with the port security policy.

Claims (31)

1. An information handling system comprising:

a host system comprising a processor;

one or more external input/output (I/O) ports;

a chipset communicatively coupled to the processor and including an I/O port controller, the I/O port controller being configured to interface between the processor and the one or more external I/O ports; and

a management controller communicatively coupled to the processor configured to provide out-of-band management of the information handling system, and further configured to communicate a port security policy to a component of the chipset such that the I/O port controller is configured to dynamically enable or disable, independent of an operating state of the host system, individual ones of the one or more external I/O ports in accordance with the port security policy, wherein the I/O port controller is further configured to enable no more than a maximum number of the one or more external I/O ports, wherein the maximum number is specified by the port security policy.

2. The information handling system of claim 1 , wherein the chipset comprises the management controller.

3. The information handling system of claim 1 , wherein the component of the chipset includes a port security policy engine interfaced between the I/O port controller and the management controller and configured to control the I/O port controller to dynamically enable or disable the individual ones of the one or more external I/O ports in accordance with the port security policy.

4. The information handling system of claim 1 , wherein the one or more external I/O ports comprise Universal Serial Bus (USB) ports and the I/O port controller comprises a USB controller.

5. The information handling system of claim 1 , wherein the I/O port controller is configured to conditionally enable at least one external I/O port of the one or more external I/O ports such that an external I/O device coupled to the at least one external I/O port is permitted to communicate with the processor only if the external I/O device is within one or more permitted classes of devices set forth in the port security policy.

6. The information handling system of claim 1 , wherein the I/O port controller is configured to conditionally enable at least one external I/O port of the one or more external I/O ports such that an external I/O device coupled to the at least one external I/O port is permitted to communicate with the processor only if the external I/O device has one or more particular identifying characteristics as set forth in the port security policy.

7. The information handling system of claim 6 , wherein the particular identifying characteristics comprise at least one of an identifier of the external I/O device or a certificate associated with the external I/O device.

8. The information handling system of claim 1 , wherein the I/O port controller is configured to disable an enablement or a conditional enablement of at least one external I/O port of the one or more external I/O ports in accordance with a temporal limitation of the enablement or conditional enablement as set forth in the port security policy.

9. The information handling system of claim 1 , wherein the I/O port controller is configured to disable an enablement or a conditional enablement of at least one external I/O port of the one or more external I/O ports in response to disconnection of an external I/O device from the at least one external I/O port as set forth in the port security policy.

10. The information handling system of claim 1 , wherein the I/O port controller is further configured to disable individual ones of the one or more external I/O ports in accordance with a maximum hub depth of the one or more external I/O ports as set forth in the port security policy.

11. A method comprising:

dynamically enabling or disabling, independent of an operating state of a host system of an information handling system, individual ones of one or more external input/output (I/O) ports of the host system in accordance with a port security policy, wherein the dynamically enabling or disabling includes enabling no more than a maximum number of the one or more external I/O ports, wherein the maximum number is specified by the port security policy;

wherein the host system includes:

a processor; and

a chipset communicatively coupled to the processor and including an I/O port controller, the I/O port controller being configured to interface between the processor and the one or more external I/O ports.

12. The method of claim 11 , wherein the one or more external I/O ports comprise Universal Serial Bus (USB) ports and the I/O port controller comprises a USB controller.

13. The method of claim 11 , further comprising conditionally enabling at least one external I/O port of the one or more external I/O ports such that an external I/O device coupled to the at least one external I/O port is permitted to communicate with the processor only if the external I/O device is within one or more permitted classes of devices set forth in the port security policy.

14. The method of claim 11 , further comprising conditionally enabling at least one external I/O port of the one or more external I/O ports such that an external I/O device coupled to the at least one external I/O port is permitted to communicate with the processor only if the external I/O device has one or more particular identifying characteristics as set forth in the port security policy.

15. The method of claim 14 , wherein the particular identifying characteristics comprise at least one of an identifier of the external I/O device or a certificate associated with the external I/O device.

16. The method of claim 11 , further comprising disabling an enablement or a conditional enablement of at least one external I/O port of the one or more external I/O ports in accordance with a temporal limitation of the enablement or conditional enablement as set forth in the port security policy.

17. The method of claim 11 , further comprising disabling an enablement or a conditional enablement of at least one external I/O port of the one or more external I/O ports in response to disconnection of an external I/O device from the at least one external I/O port as set forth in the port security policy.

18. The method of claim 11 , further comprising disabling individual ones of the one or more external I/O ports in accordance with a maximum hub depth of the one or more external I/O ports as set forth in the port security policy.

19. An information handling system comprising:

a host system comprising a processor;

one or more external input/output (I/O) ports;

a chipset communicatively coupled to the processor and including an I/O port controller, the I/O port controller being configured to interface between the processor and the one or more external I/O ports; and

a management controller communicatively coupled to the processor configured to provide out-of-band management of the information handling system, and further configured to communicate a port security policy to a component of the chipset such that the I/O port controller is configured to dynamically enable or disable, independent of an operating state of the host system, individual ones of the one or more external I/O ports in accordance with the port security policy, wherein the I/O port controller is further configured to enable only those ones of the one or more external I/O ports having hub depths that are in accordance with a maximum hub depth specified by the port security policy.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040679/0386) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0666 →
RELEASE OF SECURITY INTEREST AT REEL 040633 FRAME 0799 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL INTERNATIONAL, L.L.C.; DELL PRODUCTS L.P.; WYSE TECHNOLOGY L.L.C.; EMC CORPORATION
Reel/Frame 058297/0427 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Nov 23, 2016
From: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; WYSE TECHNOLOGY L.L.C.; EMC CORPORATION
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 040679/0386 →
SECURITY INTEREST Recorded Nov 16, 2016
From: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; WYSE TECHNOLOGY L.L.C.; EMC CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040633/0799 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2016
From: LAMBERT, TIMOTHY M.; KHATRI, MUKUND P.
To: DELL PRODUCTS L.P.
Reel/Frame 039346/0909 →
Continuity (1)
Related Publication 20180039797A1 · Feb 8, 2018