IP Library Granted Patent US 9,781,226
Granted Patent B2
US 9,781,226 · App. 15/229,297 · Granted Oct 3, 2017

System and method for cache management

Inventors: Philip Derbeko (Modiin, IL); Anat Eyal (Tel Aviv, IL); Arieh Don (Newton, MA); Zvi Gabriel Benhanokh (Tel Aviv, IL); Alex Veprinsky (Brookline, MA)
Assignee: EMC IP Holding Company LLC
H04L67/2842G06F12/0804G06F12/0846G06F12/0868G06F12/0871G06F12/0897H04L47/25H04L47/822H04L67/1097H04L67/42G06F2212/1016G06F2212/1032G06F2212/262G06F2212/283G06F2212/311G06F2212/313
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Quick Facts
Patent No.
US 9,781,226
App. No.
15/229,297
Granted
Oct 3, 2017
Kind
B2
Abstract

A method, computer program product, and computing system for processing one or more data chunks on a host server. The one or more data chunks are destined for storage within a portion of a data array coupled to the host server. The one or more data chunks are stored within a host cache system included within the host server. Storage criteria concerning the portion of a data array is reviewed. The storage criteria includes an array bandwidth allotment that defines a maximum bandwidth between the host server and the portion of the data array. The one or more data chunks are written to the portion of the data array based, at least in part, upon the storage criteria.

Claims (45)

1. A computer-implemented method comprising:

processing one or more data chunks on a host server, wherein the one or more data chunks are to be stored within a portion of a data array, wherein the data array is coupled to the host server;

storing the one or more data chunks within a host cache system included within the host server;

reviewing a storage criteria concerning the portion of a data array, wherein the storage criteria includes an array bandwidth allotment that is a maximum bandwidth between the host server and the portion of the data array; and

writing the one or more data chunks from the host cache system to the portion of the data array based, at least in part, upon the storage criteria, including writing the one or more data chunks from the host cache system to the portion of the data array if bandwidth exists of the maximum bandwidth between the host server and the portion of the data array, and if bandwidth does not exist of the maximum bandwidth between the host server and the portion of the data array, then modifying the write sequence based, at least in part, upon the array bandwidth allotment.

2. The computer-implemented method of claim 1 wherein writing the one or more data chunks to the portion of the data array based, at least in part, upon the storage criteria includes writing the one or more data chunks from the host cache system to the portion of the data array in an order based upon, at least in part, an amount of time the one or more data chunks have been stored within the host cache system.

3. The computer-implemented method of claim 1 wherein the storage criteria further includes a maximum storage delay that is a maximum amount of time that the one or more data chunks may be stored within the host cache system before being written to the portion of the data array.

4. The computer-implemented method of claim 1 wherein the storage criteria further includes a storage device performance indicator that is a performance level for a storage device associated within the portion of the data array.

5. The computer-implemented method of claim 1 wherein:

the one or more data chunks includes a first data chunk and a second data chunk, and

writing the one or more data chunks to the portion of the data array includes:

writing the first data chunk and the second data chunk to the portion of the data array in the write sequence that is further based, at least in part, upon the storage criteria.

6. The computer-implemented method of claim 1 wherein the portion of the data array includes one or more Logical Unit Numbers (LUNs).

7. The computer-implemented method of claim 1 wherein the host cache system is a write back cache system.

8. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:

processing one or more data chunks on a host server, wherein the one or more data chunks are to be stored within a portion of a data array, wherein the data array is coupled to the host server;

storing the one or more data chunks within a host cache system included within the host server;

reviewing a storage criteria concerning the portion of a data array, wherein the storage criteria includes an array bandwidth allotment that is a maximum bandwidth between the host server and the portion of the data array; and

writing the one or more data chunks from the host cache system to the portion of the data array based, at least in part, upon the storage criteria, including writing the one or more data chunks from the host cache system to the portion of the data array if bandwidth exists of the maximum bandwidth between the host server and the portion of the data array, and if bandwidth does not exist of the maximum bandwidth between the host server and the portion of the data array, then modifying the write sequence based, at least in part, upon the array bandwidth allotment.

9. The computer program product of claim 8 wherein writing the one or more data chunks to the portion of the data array based, at least in part, upon the storage criteria includes writing the one or more data chunks from the host cache system to the portion of the data array in an order based upon, at least in part, an amount of time the one or more data chunks have been stored within the host cache system.

10. The computer program product of claim 8 wherein the storage criteria further includes a maximum storage delay that is a maximum amount of time that the one or more data chunks may be stored within the host cache system before being written to the portion of the data array.

11. The computer program product of claim 8 wherein the storage criteria further includes a storage device performance indicator that is a performance level for a storage device associated within the portion of the data array.

12. The computer program product of claim 8 wherein:

the one or more data chunks includes a first data chunk and a second data chunk, and

the instructions for writing the one or more data chunks to the portion of the data array include instructions for:

writing the first data chunk and the second data chunk to the portion of the data array in the write sequence that is further based, at least in part, upon the storage criteria.

13. The computer program product of claim 8 wherein the portion of the data array includes one or more Logical Unit Numbers (LUNs).

14. The computer program product of claim 8 wherein the host cache system is a write back cache system.

15. A computing system comprising:

at least one processor device; and

at least one memory architecture coupled with the at least one processor device;

wherein the at least one processor device is further configured to perform operations comprising;

processing one or more data chunks on a host server, wherein the one or more data chunks are to be stored within a portion of a data array, wherein the data array is coupled to the host server;

storing the one or more data chunks within a host cache system included within the host server;

reviewing storage criteria concerning the portion of a data array, wherein the storage criteria includes an array bandwidth allotment that is a maximum bandwidth between the host server and the portion of the data array; and

writing the one or more data chunks from the host cache system to the portion of the data array based, at least in part, upon the storage criteria, including writing the one or more data chunks from the host cache system to the portion of the data array if bandwidth exists of the maximum bandwidth between the host server and the portion of the data array, and if bandwidth does not exist of the maximum bandwidth between the host server and the portion of the data array, then modifying the write sequence based, at least in part, upon the array bandwidth allotment.

16. The computing system of claim 15 wherein writing the one or more data chunks to the portion of the data array based, at least in part, upon the storage criteria includes writing the one or more data chunks from the host cache system to the portion of the data array in an order based upon, at least in part, an amount of time the one or more data chunks have been stored within the host cache system.

17. The computing system of claim 15 wherein the storage criteria further includes a maximum storage delay that is a maximum amount of time that the one or more data chunks may be stored within the host cache system before being written to the portion of the data array.

18. The computing system of claim 15 wherein the storage criteria further includes a storage device performance indicator that is a performance level for a storage device associated within the portion of the data array.

19. The computing system of claim 15 wherein:

the one or more data chunks includes a first data chunk and a second data chunk, and

writing the one or more data chunks to the portion of the data array includes:

writing the first data chunk and the second data chunk to the portion of the data array in the write sequence that is further based, at least in part, upon the storage criteria.

20. The computing system of claim 15 wherein the portion of the data array includes one or more Logical Unit Numbers (LUNs).

21. The computing system of claim 15 wherein the host cache system is a write back cache system.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (041829/0873) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0724 →
RELEASE OF SECURITY INTEREST AT REEL 041808 FRAME 0516 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL INTERNATIONAL, L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058297/0573 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY INTEREST (NOTES) Recorded Feb 28, 2017
From: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 041829/0873 →
PATENT SECURITY INTEREST (CREDIT) Recorded Feb 24, 2017
From: DELL INTERNATIONAL, L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 041808/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2016
From: DERBEKO, PHILIP; EYAL, ANAT; BENHANOKH, ZVI GABRIEL
To: EMC CORPORATION
Reel/Frame 039352/0243 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2016
From: DON, ARIEH; VEPRINKSY, ALEX
To: EMC CORPORATION
Reel/Frame 039352/0086 →
Continuity (2)
Continuation 13731415 · Dec 31, 2012
Related Publication 20160344837A1 · Nov 24, 2016