Apparatus and method for forward error correction over a communication channel
View Patent ↗There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).
1. An OTN (Optical Transport Network) system comprising:
an OTN transmitter comprising (i) an OTN framer device configured to generate an OTN frame having FEC (Forward Error Correction) parity, (ii) an FEC encoder circuit configured to remove the FEC parity from the OTN frame, re-structure data from the OTN frame, create new FEC parity locations, and generate FEC parity for the new parity locations thereby generating an FEC encoded frame, and (iii) a transmitting OTL (Optical channel Transport Lane) configured to transmit the FEC encoded frame over a communication channel;
an OTN backplane through which the communication channel traverses; and
an OTN receiver comprising (i) a receiving OTL configured to receive the FEC encoded frame over the communication channel, and (ii) an FEC decoding circuit configured to decode the FEC encoded frame to recover the data;
wherein the FEC encoder circuit is configured to generate the FEC parity for the new parity locations in a manner that compensates for bit shuffling performed by the transmitting OTL.
2. The OTN system of claim 1 , wherein the FEC encoder circuit is configured to generate the FEC parity while compensating for bit shuffling done by the transmitting OTL such that data striping is achieved at a symbol level across physical lanes of the communication channel despite inverse multiplexing of the FEC encoded frame by the transmitting OTL.
3. The OTN system of claim 2 , wherein the FEC encoder circuit is configured to compensate for bit shuffling done by the transmitting OTL by bit shuffling the data before generating the FEC parity and by bit de-shuffling after generating the FEC parity.
4. The OTN system of claim 3 , wherein:
bit shuffling the data before generating the FEC parity comprises, for each group of 20×128 bits (bit[LL][n], LL=0..19, n=0..127), mapping the group into 256 10-bit symbols (symbol[S][m], s=0..255, m=0..9) as follows:
symbol[ S][m] ← bit[ LL][n]
S= 4*floor( n/ 2)+floor( LL/ 5)
m= 5*( n mod 2)+( LL mod 5); and
bit de-shuffling the data after generating the FEC parity comprises, for each group of 256 10-bit symbols (symbol[S][m], s=0..255, m=0..9), mapping the group into 20×128 bits (bit[LL][n], LL=0..19, n=0..127) as follows:
bit[ LL][n] ←symbol[ S][m]
LL= 5*( S mod 4)+( m mod 5)
n= 2*floor( S/ 4)+floor( m/ 5).
5. The OTN system of claim 1 , wherein the FEC encoder circuit comprises an RS (Reed Solomon) encoder for generating the FEC parity.
6. The OTN system of claim 5 , wherein the FEC encoder circuit is configured to re-structure the OTN frame, which is initially structured with sixteen RS (255,239,m=8,t=8) per OTN frame row, into a new FEC structure having five RS (627,613,m=10,t=7) per OTN frame row.
7. The OTN system of claim 5 , wherein the FEC encoder circuit is configured to re-structure the OTN frame, which is initially structured with sixteen RS (255,239,m=8,t=8) per OTN frame row, into a new FEC structure having fifteen RS (528,514,m=10,t=7) per OTN frame row.
8. The OTN system of claim 5 , wherein the FEC encoder circuit is configured to re-structure the OTN frame, which is initially structured with sixteen RS (255,239,m=8,t=8) per OTN frame row, into a new FEC structure having thirty-two RS (970,956,m=10,t=7) per OTN frame row.
9. The OTN system of claim 1 , wherein the FEC encoder circuit is configured to remove FAS (Frame Alignment Signal) bytes from the OTN frame and insert new FAS bytes into the OTN frame.
10. A method for communicating data in an OTN (Optical Transport Network) system, the method comprising:
generating an OTN frame having FEC (Forward Error Correction) parity;
removing the FEC parity from the OTN frame;
re-structuring data from the OTN frame;
creating new FEC parity locations;
generating FEC parity for the new parity locations thereby generating an FEC encoded frame;
transmitting, by a transmitting OTL (Optical channel Transport Lane), the FEC encoded frame over a communication channel;
receiving the FEC encoded frame over the communication channel; and
decoding the FEC encoded frame to recover the data;
wherein generating the FEC parity for the new parity locations is performed in a manner that compensates for bit shuffling performed by the transmitting OTL.
11. The method of claim 10 , comprising:
generating the FEC parity while compensating for bit shuffling done by the transmitting OTL such that data striping is achieved at a symbol level across physical lanes of the communication channel despite inverse multiplexing of the FEC encoded frame by the transmitting OTL.
12. The method of claim 11 , wherein compensating for bit shuffling done by the transmitting OTL comprises:
bit shuffling the data before generating the FEC parity; and
bit de-shuffling after generating the FEC parity.
13. The method of claim 12 , wherein:
bit shuffling the data before generating the FEC parity comprises, for each group of 20×128 bits (bit[LL][n], LL=0..19, n=0..127), mapping the group into 256 10-bit symbols (symbol[S][m], s=0..255, m=0..9) as follows:
symbol[ S][m] ←bit[ LL][n]
S= 4*floor( n/ 2)+floor( LL/ 5)
m= 5*( n mod 2)+( LL mod 5); and
bit de-shuffling the data after generating the FEC parity comprises, for each group of 256 10-bit symbols (symbol[S][m], s=0..255, m=0..9), mapping the group into 20×128 bits (bit[LL][n], LL=0..19, n=0..127) as follows:
bit[ LL][n ]←symbol[ S][m]
LL= 5*( S mod 4)+( m mod 5)
n= 2*floor( S/ 4)+floor( m/ 5).
14. The method of claim 10 , wherein generating the FEC parity comprises an RS (Reed Solomon) encoder generating the FEC parity.
15. The method of claim 14 , comprising:
re-structuring the OTN frame, which is initially structured with sixteen RS (255,239,m=8,t=8) per OTN frame row, into a new FEC structure having five RS (627,613,m=10,t=7) per OTN frame row.
16. The method of claim 14 , comprising:
re-structuring the OTN frame, which is initially structured with sixteen RS(255,239,m=8,t=8) per OTN frame row, into a new FEC structure having fifteen RS (528,514,m=10,t=7) per OTN frame row.
17. The method of claim 14 , comprising:
re-structuring the OTN frame, which is initially structured with sixteen RS(255,239,m=8,t=8) per OTN frame row, into a new FEC structure having thirty-two RS (970,956,m=10,t=7) per OTN frame row.
18. The method of claim 10 , further comprising:
removing FAS (Frame Alignment Signal) bytes from the OTN frame; and
inserting new FAS bytes into the OTN frame transmission by the transmitting OTL.
19. An OTN (Optical Transport Network) transmitter comprising:
a framer device configured to generate an OTN frame having FEC (Forward Error Correction) parity;
re-structuring circuitry configured to remove the FEC parity from the OTN frame, re-structure data from the OTN frame, and create new FEC parity locations;
coding circuitry configured to generate FEC parity for the new parity locations thereby generating an FEC encoded frame; and
a transmitting OTL (Optical channel Transport Lane) configured to transmit the FEC encoded frame;
wherein the coding circuitry is configured to generate the FEC parity in a manner that compensates for bit shuffling performed by the transmitting OTL.
20. The OTN transmitter of claim 19 , comprising:
an FPGA (Field Programmable Gate Array) implementing at least the framer device.