Semiconductor device and method of manufacturing the same
View Patent ↗A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged in a first direction. The semiconductor device may include second channel layers adjacent to the first channel layers in a second direction crossing the first direction and arranged in the first direction. The semiconductor device may include insulating layers stacked while surrounding side walls of the first and second channel layers. The semiconductor device may include conductive layers interposed between the insulating layers, and including first metal patterns extended in the first direction and second metal patterns extended in the first direction while surrounding the side walls of the first channel layers.
1. A method of manufacturing a semiconductor device, comprising:
alternately forming first material layers and second material layers;
forming first openings passing through the first and second material layers, and arranged in a first direction and a second direction crossing the first direction;
forming a sacrificial layer within the first openings;
forming a slit passing through the first and second material layers and extended in the first direction;
forming second openings by removing the first material layers through the slit; and
forming first metal patterns for gate electrodes within the second openings;
forming third openings by removing the first material layers through the first openings;
forming second metal patterns for gate electrodes within the third openings, respectively;
forming memory layers within the first openings; and
forming channel layers within the memory layers.
2. The method of claim 1 , further comprising: forming first barrier patterns surrounding a whole surface of the second metal patterns, respectively.
3. The method of claim 2 , wherein the first barrier patterns include at least one of titanium (Ti), a titanium nitride (TiN), tantalum (Ta), a tantalum nitride (TaN), a tungsten nitride (WNx), or a tungsten silicon nitride (WSiN).
4. The method of claim 1 ,
wherein the third openings are formed to expose the sacrificial layer .
5. The method of claim 1 ,
wherein the second openings are formed by partially removing the first material layers.
6. The method of claim 5 , wherein the forming of the second openings only partially removes the first material layers to prevent exposure of the sacrificial layer.
7. The method of claim 5 , further comprising:
forming second barrier patterns within the second openings before the forming of the first metal patterns.
8. The method of claim 7 , wherein the second barrier patterns include at least one of titanium (Ti), a titanium nitride (TiN), tantalum (Ta), a tantalum nitride (TaN), a tungsten nitride (WNx), or a tungsten silicon nitride (WSiN).
9. The method of claim 7 , wherein each of the second barrier patterns surrounds each of the first metal patterns, and is interposed between corresponding first metal pattern and the second material layers and between the corresponding first metal pattern and corresponding channel layer.
10. The method of claim 7 , wherein the second barrier patterns surround a side wall, an upper surface, and a lower surface of the first metal patterns, respectively.
11. The method of claim 5 , further comprising:
forming a slit insulating layer within the slit after the forming of the first metal patterns.
12. The method of claim 1 , wherein the first metal patterns include aluminum (Al), tungsten (W), or copper (Cu).
13. The method of claim 1 , wherein the first material layers have a higher etch selectivity than the second material layers.
14. A method of manufacturing a semiconductor device, comprising
alternately forming first material layers and second material layers;
forming first openings passing through the first and second material layers, and arranged in a first direction and a second direction crossing the first direction;
forming second openings by removing the first material layers through the first openings;
forming first metal patterns for gate electrodes within the second openings, respectively;
forming memory layers within the first openings;
forming channel layers within the memory layers;
forming a slit passing through the first and second material layers and extended in the first direction;
forming third openings by removing the remaining first material layers through the slit; and
forming second metal patterns for gate electrodes within the third openings.
15. The method of claim 14 , further comprising:
forming second barrier patterns within the third openings before the forming of the second metal patterns.
16. The method of claim 15 , wherein the second barrier patterns include titanium (Ti), a titanium nitride (TiN), tantalum (Ta), a tantalum nitride (TaN), a tungsten nitride (WNx), or a tungsten silicon nitride (WSiN).
17. The method of claim 15 , wherein each of the second barrier patterns surrounds each of the second metal patterns, and is interposed between a corresponding second metal pattern and the second material layers and between the corresponding second metal pattern and a corresponding channel layer.
18. The method of claim 15 , wherein the second barrier patterns surround a side wall, an upper surface, and a lower surface of the second metal patterns, respectively.
19. The method of claim 14 , further comprising:
forming a slit insulating layer within the slit after the forming of the second metal patterns.
20. A method of manufacturing a semiconductor device, comprising:
alternately forming first material layers and second material layers;
forming channel holes passing through the first and second material layers;
forming a sacrificial layer within the channel holes;
forming a slit passing through the first and second material layers;
forming first openings by removing the first material layers through the slit to expose the sacrificial layer; and
forming first gate electrodes within the first openings;
forming second openings by removing the first material layers through the channel holes;
forming second gate electrodes within the second openings, respectively;
forming memory layers within the channel holes; and
forming channel layers within the channel holes where the memory layers are formed.