Semiconductor memory and method of manufacturing the same
A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
1. A semiconductor memory device comprising:
a semiconductor substrate including a first part having a first upper surface;
a plurality of first stacks of layers arranged along a first direction perpendicular to the first upper surface above the first upper surface and extending in a second direction parallel to the first upper surface, each of the plurality of first stacks of layers including a first semiconductor layer;
a plurality of second stacks of layers arranged along the first direction above the first upper surface and extending in the second direction, the plurality of second stacks of layers being adjacent to the plurality of first stacks of layers in a third direction parallel to the first upper surface, the third direction intersecting the second direction, each of the plurality of second stacks of layers including a second semiconductor layer;
a conductive layer disposed on the plurality of first stacks of layers and the plurality of second stacks of layers and covering the plurality of first stacks of layers and the plurality of second stacks of layers;
first memory portions disposed, in the third direction, between the conductive layer and first side surfaces of the first semiconductor layers, the first side surfaces being perpendicular to the first upper surface;
second memory portions disposed, in the third direction, between the conductive layer and second side surfaces of the second semiconductor layers, the second side surfaces being perpendicular to the first upper surface; and
a first selection transistor disposed on the first semiconductor layer of one of the plurality of first stacks of layers,
wherein the first selection transistor includes a gate electrode on the first semiconductor layer of the one of the plurality of first stacks of layers,
the gate electrode is covered with a second upper surface of the first semiconductor layer of the one of the plurality of first stacks of layers and the first side surfaces of the first semiconductor layer of the one of the plurality of first stacks of layers via a gate insulating layer.
2. The device according to claim 1 , further comprising:
a first contact portion electrically connected to a first end portion of the first semiconductor layer of the one of the plurality of first stacks of layers in the second direction,
wherein the first contact portion is disposed between the first selection transistor and the first end portion.
3. The device according to claim 2 , further comprising:
a second selection transistor disposed on the first semiconductor layer of the other of the plurality of first stacks of layers, the first semiconductor layer of the other of the plurality of first stacks of layers arranged below the first semiconductor layer of the one of the plurality of first stacks of layers in the first direction; and
a second contact portion electrically connected to a second end portion of the first semiconductor layer of the other of the plurality of first stacks of layers in the second direction,
wherein the second contact portion is disposed between the second selection transistor and the second end portion, and
a first distance between the second contact portion and the second selection transistor in the second direction is shorter than a second distance between the second contact portion and the first selection transistor in the second direction.
4. The device according to claim 3 , wherein
a first length of the first semiconductor layer of the other of the plurality of first stacks of layers in the second direction is longer than a second length of the first semiconductor layer of the one of the plurality of first stacks of layers in the second direction.
5. The device according to claim 2 , further comprising:
a second contact portion electrically connected to second end portions of the first semiconductor layers in the second direction,
wherein the second end portions are opposed to the first end portion in the second direction.
6. The device according to claim 1 , further comprising:
a second selection transistor disposed on the second semiconductor layer of one of the plurality of second stacks of layers,
wherein a gate electrode of the second selection transistor is electrically connected to a gate electrode of the first selection transistor, and
a first distance between a third upper surface of the second semiconductor layer of the one of the plurality of second stacks of layers and a first under surface of the semiconductor substrate is equal to a second distance between the first upper surface of the first semiconductor layer of the one of the plurality of first stacks of layers and the first under surface of the semiconductor substrate.
7. The device according to claim 6 , further comprising:
an electrode layer extending in the third direction and disposed across the first semiconductor layer of the one of the plurality of first stacks of layers and the second semiconductor layer of the one of the plurality of second stacks of layers,
wherein the electrode layer includes the gate electrode of the second selection transistor and the gate electrode of the first selection transistor.
8. The device according to claim 7 , wherein
a portion of the electrode layer is disposed between the first side surface of the first semiconductor layer of the one of the plurality of first stacks of layers and the second side surface of the second semiconductor layer of the one of the plurality of second stacks of layers.
9. The device according to claim 1 , wherein:
first end portions of the plurality of first stacks of layers have a stair shape.
10. The device according to claim 1 , further comprising:
a peripheral circuit disposed on a third upper surface of a second part included in the semiconductor substrate,
wherein a first distance between the first upper surface and a first under surface of the semiconductor substrate is shorter than a second distance between the third upper surface and the first under surface.
11. The device according to claim 1 , wherein
each of the first memory portions includes a memory layer disposed between the conductive layer and the first side surfaces.
12. The device according to claim 11 , wherein
the memory layer is continuous between a first under surface of the plurality of first stacks of layers and a third upper surface of the plurality of first stacks of layers in the first direction.
13. The device according to claim 11 , wherein
the memory layer includes, a first insulating layer, a second insulating layer, and a charge storage layer between the first insulating layer and the second insulating layer,
the first insulating layer is disposed between the charge storage layer and the first side surfaces, and
the second insulating layer is disposed between the charge storage layer and the conductive layer.
14. The device according to claim 11 , wherein
the memory layer includes a chalcogenide layer.
15. The device according to claim 11 , wherein
the memory layer includes a resistance change layer.
16. The device according to claim 1 , wherein
the conductive layer extends in the first direction.
17. The device according to claim 1 , wherein
a conductive layer is disposed between the first side surfaces and the second surfaces.
18. The device according to claim 1 , wherein
each of the plurality of the first stacks of layers include a first insulating layer,
wherein the first insulating layers and the first semiconductor layers are alternately stacked in the first direction.