IP Library Granted Patent US 9,941,165
Granted Patent B2
US 9,941,165 · App. 15/231,717 · Granted Apr 10, 2018

Semiconductor manufacturing method

Inventors: Tatsuo Migita (Oita Oita, JP); Fumito Shoji (Oita Oita, JP); Koji Ogiso (Oita Oita, JP)
Assignee: Toshiba Memory Corporation
H01L21/76898B08B3/02H01L21/02068H01L21/02244H01L21/288H01L21/67051H01L21/687H01L21/76831H01L21/76846H01L21/76879
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Quick Facts
Patent No.
US 9,941,165
App. No.
15/231,717
Granted
Apr 10, 2018
Kind
B2
Abstract

A semiconductor manufacturing method includes forming a first metal film on a semiconductor wafer by plating, ejecting liquid from a washer bar spaced from the wafer while rotating at least one of the washer and the semiconductor, and forming a second metal film on the first metal film. A plurality of nozzles are located on the washer bar and displaced from the position of the washer bar opposed to the center of the wafer, and a greater number of nozzles are adjacent the peripheral area of the semiconductor wafer than the central area of the semiconductor wafer. The nozzles in the peripheral area of the wafer eject the washing liquid in a direction inclined from the direction of the washer bar, and a nozzle arranged on the central area of the one main surface of the semiconductor wafer ejects the washing liquid towards the center position of the semiconductor wafer.

Claims (30)

1. A semiconductor manufacturing method, comprising:

forming a first metal film on one main surface of a semiconductor wafer by a first plating treatment;

ejecting, from a washer bar spaced from the one main surface of the semiconductor wafer, a washing liquid onto the one main surface of the semiconductor wafer, while rotating at least either one of the washer bar and the semiconductor wafer to wash a surface of the first metal film;

forming a second metal film on the first metal film by a second plating treatment, wherein a plurality of nozzles are located along the washer bar in a single direction; and

forming an insulating film on an inner wall portion of a hole extending through the semiconductor wafer, wherein

the plurality of nozzles are displaced from a position of the washer bar located opposed to a center of the one main surface of the semiconductor wafer, and a greater number of nozzles are located adjacent to the peripheral area of the one main surface of the semiconductor wafer than are located adjacent to central area of the semiconductor wafer,

the nozzles located on the peripheral area of the one main surface of the semiconductor wafer eject the washing liquid in a first range along a direction inclined from one direction of the washer bar,

one of the nozzles located opposed to the central area of the one main surface of the semiconductor wafer ejects the washing liquid in a second range including the center of the semiconductor wafer,

the first metal film is formed by the first plating treatment on an inner side of the insulating film, and the second metal film formed by the second plating treatment is on an outer side of the insulating film, and

a ratio of a film thickness of the first metal film in the hole to a diameter of the hole is 15.6% or greater.

2. The semiconductor manufacturing method according to claim 1 , wherein

the one direction is a direction that intersects a normal line passing through the center of the one main surface of the semiconductor wafer, and extends in a direction parallel to the one main surface of the semiconductor wafer.

3. The semiconductor manufacturing method according to claim 2 , wherein

the same number of nozzles are located on the washer bar on one side of the normal line passing through the center position of the semiconductor wafer as are located on the other side of the normal line passing through the center position of the semiconductor wafer.

4. The semiconductor manufacturing method according to claim 3 , wherein

two or more nozzles are located to face the peripheral area of the one main surface of the semiconductor wafer on both sides of the normal line along the one direction, and each of the two or more nozzles on each side of the normal line ejects the washing liquid in a first range inclined at the same angle from the one direction.

5. The semiconductor manufacturing method according to claim 1 , wherein

the washer rotates around a rotation axis extending through the semiconductor wafer, and

the semiconductor wafer is held fixed.

6. The semiconductor manufacturing method according to claim 1 , comprising the steps of:

ejecting a washing liquid onto the one main surface from the washer after the second metal film is formed, while rotating at least one of the washer or the semiconductor wafer about an axis extending through the semiconductor wafer to wash the surface of the second metal film; and

forming a third metal film on the second metal film by a second plating treatment.

7. A method of metallizing a plurality of through silicon vias in a semiconductor wafer, comprising:

forming an insulating layer to cover sidewalls of the vias; and

plating a plurality of conductive films on the insulating layer formed on the sidewalls of the vias, wherein

a first metal film of the plurality of conductive films is formed by a first plating treatment on an inner side of the insulating layer and other metal films of the plurality of conductive films are formed by other plating treatments in a stacked manner on an outer side of the insulating layer, and

a ratio of a film thickness of a conductive film in the via to a diameter of the via is 15.6% or greater.

8. The method of claim 7 , wherein, after plating each conductive film, washing the surface of the semiconductor wafer with a uniform quantity of liquid across the surface thereof to remove plating material adhered thereto.

9. The method of claim 8 , wherein during the washing of the surface, a uniform oxidation layer is formed on the conductive film.

10. The method of claim 8 , wherein the conductive film comprises at least one of nickel, copper and tin.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: MIGITA, TATSUO; SHOJI, FUMITO; OGISO, KOJI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 041148/0467 →
Priority Claims (1)
JP 2016-050105 · Mar 14, 2016 · national
Continuity (1)
Related Publication 20170263499A1 · Sep 14, 2017