Nonvolatile memory device for suppressing read disturbances

1. A nonvolatile memory device comprising:

a nonvolatile memory cell coupled between a bit line and a ground terminal and comprising a first PMOS transistor and a second PMOS transistor;

a sensing circuit comprising a third PMOS transistor and a first NMOS transistor, wherein gates of the third PMOS transistor and the first NMOS transistor are coupled to the bit line, and drains of the third PMOS transistor and the first NMOS transistor are coupled to a sensing output line, and a source of the first NMOS transistor is coupled to the ground terminal;

a first switching portion comprising a fourth PMOS transistor having a gate to which a first enable signal is applied, a source coupled to a supply voltage line, and a drain coupled to a source of the third PMOS transistor;

a sensing output grounding portion comprising a second NMOS transistor having a gate to which a second enable signal is applied, a drain coupled to the sensing output line, and a drain coupled to the ground terminal;

a resistive load/second switching portion comprising a fifth PMOS transistor having a gate to which a third enable signal is applied, a source coupled to the supply voltage line, and a drain coupled to the bit line;

a bit line grounding portion comprising a third NMOS transistor having a gate to which a fourth enable signal is applied, a drain coupled to the bit line, and a source coupled to the ground terminal; and

an enable signal generator receiving a sensing output signal from the sensing output line and a sense amplifier enable signal, and generating the first to fourth enable signals,

wherein the enable signal generator configured to sequentially supply the first to fourth enable signal of high level if a sensing output signal of the sensing output line is changed from a high level into a low level.

2. The nonvolatile memory device of claim 1 ,

wherein the first PMOS transistor having a floating gate, a source, and a drain coupled to the ground terminal, and

the second PMOS transistor having a gate coupled to a selection enable signal line, a source coupled the bit line, and a drain coupled to the source of the first PMOS transistor.

3. The nonvolatile memory device of claim 1 , wherein the enable signal generator comprises:

a first inverter to which the sensing output signal is applied;

a first NAND gate to which an output signal from the first inverter and the sense amplifier enable signal are applied;

a second inverter to which an output signal of the first NAND gate is applied and which outputs the first enable signal;

a second NAND gate to which an output signal of the second inverter and the sense amplifier enable signal are applied;

a third inverter to which an output signal of the second NAND gate is applied and which outputs the second enable signal;

a third NAND gate to which the output signal of the second NAND gate and the sense amplifier enable signal are applied and which outputs the third enable signal;

a fourth inverter to which an output signal of the third NAND gate is applied; and

a fifth inverter to which an output signal of the fourth inverter is applied and which outputs the fourth enable signal,

wherein the sensing output signal of high level and the sense amplifier enable signal of low level are applied to the first inverter and the first NAND pate, respectively before the read operation for the nonvolatile memory cell, and

wherein the sense amplifier enable signal of high level is applied to the first NAND gate after starting the read operation for the nonvolatile memory cell.

4. The nonvolatile memory device of claim 1 ,

wherein the enable signal generator configured to sequentially supply the first enable signal of low level, the second enable signal of low level, the third enable signal of high level, and the fourth enable signal of high level before the read operation for the nonvolatile memory cell.

5. The nonvolatile memory device of claim 4 ,

wherein the enable signal generator configured to sequentially supply the first to fourth enable signals of low level, after starting the read operation for the nonvolatile memory cell.