A memory system includes first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first or second chip select signal, and first and second memory cell arrays. The interface circuit and the first and second memory cell arrays are provided in one common package, and is configured to access the first memory cell array when detecting the first chip select signal, and to access the second memory cell array when detecting the second chip select signal.
1. A memory system comprising:
first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin;
an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first chip select signal or the second chip select signal; and
a first memory cell array and a second memory cell array each comprising memory cells capable of holding data,
wherein the interface circuit, the first memory cell array, and the second memory cell array are provided in one common package,
the interface circuit includes:
a first interface circuit configured to receive the first chip select signal, the first signal, the second signal, and the clock signal, and to access the first memory cell array when detecting the first chip select signal; and
a second interface circuit configured to receive the second chip select signal, the first signal, the second signal, and the clock signal, and to access the second memory cell array when detecting the second chip select signal, and
the first interface circuit and the second interface circuit commonly share the third through fifth pins.
2. The memory system according to claim 1 , wherein
the first interface circuit is part of a first semiconductor chip,
the second interface circuit is part of a second semiconductor chip different from the first semiconductor chip,
the first memory cell array is part of a third semiconductor chip different from the first semiconductor chip and the second semiconductor chip,
the second memory cell array is part of a fourth semiconductor chip different from the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip,
the first interface circuit is configured to assert a first chip enable signal to activate the third semiconductor chip when the first chip select signal is asserted, and
the second interface circuit is configured to assert a second chip enable signal to activate the fourth semiconductor chip when the second chip select signal is asserted.
3. The memory system according to claim 2 , wherein
the first through fourth semiconductor chips are stacked in layers and sealed with a resin.
4. The memory system according to claim 1 , wherein
the first interface circuit and the first memory cell array are mounted in a first semiconductor chip, and
the second interface circuit and the second memory cell array are mounted in a second semiconductor chip.
5. The memory system according to claim 1 , wherein
the first interface circuit and the first memory cell array are mounted in a first semiconductor chip, and
the second memory cell array is mounted in a second semiconductor chip.
6. The memory system according to claim 5 , wherein
the first semiconductor chip and the second semiconductor chip are packaged by being stacked one over the other and sealed with a resin.
7. The memory system according to claim 1 , wherein
the interface circuit is part of a first semiconductor chip,
the first memory cell array is part of a second semiconductor chip different from the first semiconductor chip,
the second memory cell array is part of a third semiconductor chip different from the first semiconductor chip and the second semiconductor chip, and
the interface circuit is configured to assert a first chip enable signal to activate the second semiconductor chip when the first chip select signal is asserted, and to assert a second chip enable signal to activate the third semiconductor chip when the second chip select signal is asserted.
8. The memory system according to claim 7 , wherein
the first, second and third semiconductor chips are stacked in layers and sealed with a resin.
9. The memory system according to claim 1 , wherein
the host device is configured to read second data from the second memory cell array when having failed to read first data from the first memory cell array.
10. The memory system according to claim 1 , wherein
the host device is configured to perform verification between first data read from the first memory cell array and second data read from the second memory cell array, and execute the first data or the second data according to a result of the verification.
11. The memory system according to claim 10 , wherein
the first data and the second data are identical, and are a boot program for the host device.
12. The memory system according to claim 1 , wherein
the interface circuit is configured to receive the second signal in synchronization with the clock signal, and recognize, as the command, the first second signal received in synchronization with the clock signal received after the first select signal or the second chip select signal is asserted.
13. The memory system according to claim 1 , wherein
the interface circuit is connectable to the host device via a bus conforming to a Serial Peripheral Interface (SPI).
14. A method of operating a semiconductor device having first through fifth pins connectable to a host device for outputting to the host device a first signal through the third pin and for receiving from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first chip select signal or the second chip select signal, and a first memory cell array and a second memory cell array each comprising memory cells capable of holding data, wherein the interface circuit, the first memory cell array, and the second memory cell array are provided in one common package, and the interface circuit includes: a first interface circuit configured to receive the first chip select signal, the first signal, the second signal, and the clock signal, and to access the first memory cell array; and a second interface circuit configured to receive the second chip select signal, the first signal, the second signal, and the clock signal, and to access the second memory cell array, and the first interface circuit and the second interface circuit commonly share the third through fifth pins, said method comprising:
upon detecting the first chip select signal using the first interface circuit, accessing the first memory cell array using the first interface circuit; and
upon detecting the second chip select signal using the second interface circuit, accessing the second memory cell array using the second interface circuit.
15. The method according to claim 14 , wherein
the first interface circuit is part of a first semiconductor chip,
the second interface circuit is part of a second semiconductor chip different from the first semiconductor chip,
the first memory cell array is part of a third semiconductor chip different from the first semiconductor chip and the second semiconductor chip,
the second memory cell array is part of a fourth semiconductor chip different from the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip,
the first interface circuit is configured to assert a first chip enable signal to activate the third semiconductor chip when the first chip select signal is asserted, and
the second interface circuit is configured to assert a second chip enable signal to activate the fourth semiconductor chip when the second chip select signal is asserted.
16. The method according to claim 15 , wherein the first through fourth semiconductor chips are stacked in layers and sealed with a resin.
17. The method according to claim 14 , further comprising:
the interface circuit is part of a first semiconductor chip,
the first memory cell array is part of a second semiconductor chip different from the first semiconductor chip,
the second memory cell array is part of a third semiconductor chip different from the first semiconductor chip and the second semiconductor chip, and
the interface circuit is configured to assert a first chip enable signal to activate the second semiconductor chip when the first chip select signal is asserted, and to assert a second chip enable signal to activate the third semiconductor chip when the second chip select signal is asserted.
18. The method according to claim 17 , wherein the first, second and third semiconductor chips are stacked in layers and sealed with a resin.