Semiconductor memory device
A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.
1. A semiconductor memory device comprising:
first and second memory cells, each of which includes a charge storage layer;
a first bit line that is connected to the first memory cell; and
a second bit line that is connected to the second memory cell, wherein
a writing operation includes multiple loops of a programming operation and a verification operation,
first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation, and
in a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a second voltage is applied to the first bit line and a third voltage lower than the second voltage is applied to the second bit line during a verification operation relating to the first data.
2. The device according to claim 1 , further comprising:
a first word line that is connected to gates of the first and second memory cells, wherein
during the verification operation of the first loop, a fourth voltage for verifying the first data is applied to the first word line, and a fifth voltage for verifying the second data is not applied to the first word line.
3. The device according to claim 2 , wherein
the first voltage is applied to the second bit line during a programming operation of a second loop of the programming operation to be executed after the first loop, and the fifth voltage is applied to the first word line during a verification operation of the second loop, to perform a verification operation relating to the second data.
4. The device according to claim 1 , wherein
a threshold voltage value of a memory cell holding the second data is larger than a threshold voltage value of a memory cell holding the first data.
5. The device according to claim 1 , further comprising:
a third memory cell that includes a charge storage layer and connected to the first bit line;
a first selection transistor that is connected between the first memory cell and the first bit line; and
a second selection transistor that is connected between the third memory cell and the first bit line, wherein
during a programming operation of the first loop, a fourth voltage is applied to a gate of the first selection transistor, and a fifth voltage lower than the fourth voltage is applied to a gate of the second selection transistor, and
during a programming operation of a second loop of the writing operation to be executed after the first loop, a sixth voltage higher than the fourth voltage is applied to a gate of the first selection transistor, and a seventh voltage which is higher than the fifth voltage and is lower than the fourth voltage and the sixth voltage is applied to a gate of the second selection transistor.
6. The device according to claim 5 , wherein
the fifth voltage and the seventh voltage turn the second selection transistor off.
7. The device according to claim 1 , wherein the third voltage is ground voltage.
8. The device according to claim 1 , wherein a fourth voltage higher than the first voltage is applied to the second bit line to maintain the second bit line in the electrically floating state during the programming operation.
9. The device according to claim 8 , wherein
during a programming operation of a second loop of the writing operation to be executed after the first loop, a fifth voltage higher than the fourth voltage is applied to the second bit line, and
during a programming operation of a third loop of the writing operation to be executed after the second loop, the first voltage is applied to the second bit line.
10. The device according to claim 9 , wherein the fifth voltage applied to the second bit line inhibits programming of any memory cell connected to the second bit line.
11. The device according to claim 10 , wherein
during a verification operation of the second loop of the writing operation, the third voltage is applied to the second bit line, and
during a verification operation of the third loop of the writing operation, the second is applied to the second bit line.
12. The device according to claim 8 , wherein
during a programming operation of a second loop of the writing operation to be executed after the first loop, the first voltage is applied to the second bit line, and
during a programming operation of a third loop of the writing operation to be executed after the second loop, the first voltage is applied to the second bit line.
13. The device according to claim 12 , wherein
during a verification operation of the second loop of the writing operation, the third voltage is applied to the second bit line, and
during a verification operation of the third loop of the writing operation, the second voltage is applied to the second bit line.