Semiconductor memory device
A semiconductor memory device includes a first block that includes a first set of word lines, a second block that includes a second set of word lines and is adjacent to the first block in a first direction, a first transistor group adjacent to the first and second blocks in a second direction crossing the first direction, and a second transistor group adjacent to the first transistor group in the second direction. Each of the word lines in the first set is electrically connected to a transistor in the first transistor group, and each of the word lines in the second set is electrically connected to a transistor in the first transistor group.
1. A semiconductor memory device comprising:
a first block that includes a first set of word lines;
a second block that includes a second set of word lines and is adjacent to the first block in a first direction;
a first transistor group adjacent to the first and second blocks in a second direction crossing the first direction, wherein each of the word lines in the first set is electrically connected to a transistor in the first transistor group; and
a second transistor group adjacent to the first transistor group in the second direction, wherein each of the word lines in the second set is electrically connected to a transistor in the second transistor group.
2. The device according to claim 1 , wherein
the first set of word lines includes first and second word lines electrically connected respectively to first and second transistors, which are transistors in the first transistor group, and the second set of word lines includes third and fourth word lines electrically connected respectively to third and fourth transistors, which are transistors in the second transistor group, and
the first and second transistors are adjacent to each other in the first direction, and the third and fourth transistors are adjacent to each other in the first direction.
3. The device according to claim 2 , wherein the first set of word lines includes a fifth word line electrically connected to a fifth transistor in the first transistor group, that is adjacent to the first transistor in the second direction.
4. The device according to claim 2 , further comprising:
an element isolation area between the first transistor and the second transistor, and between the third transistor and the fourth transistor.
5. The device according to claim 1 , further comprising:
a third block that includes a third set of word lines and is adjacent to the second block in the first direction,
wherein each of the word lines in the third set is electrically connected to a transistor in the first transistor group.
6. The device according to claim 1 , further comprising:
a third block that includes a third set of word lines and is adjacent to the second block in the first direction,
wherein each of the word lines in the third set is electrically connected to a transistor in the second transistor group.
7. The device according to claim 5 , wherein connection terminals between the word lines in the first set and the transistors in the first transistor group are located within a width of the first block in the first direction.
8. The device according to claim 1 , further comprising:
a third block that includes a third set of word lines and is adjacent to the second block in the first direction; and
a third transistor group adjacent to the second transistor group in the second direction, wherein each of the word lines in the third set is electrically connected to a transistor in the third transistor group.
9. The device according to claim 1 , further comprising:
a shield gate between the first and second transistor groups.