High frequency delay lock loop systems
The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.
1. A method for operating a delay lock loop (DLL) system, the method comprising:
receiving a square clock signal;
maintaining an edge shape of the square clock signal;
generating n output signals using a delay line and the square clock signal, the n output signals including a first phase signal and a last phase signal;
determining an accumulated phase offset using the first phase signal and the last phase signal;
determining a reference phase offset using two adjacent output signals of the n output signals;
generating a correctional signal using at least the accumulated phase offset and the reference phase offset;
generating a first bias voltage and a second bias voltage using at least the correction signal.
2. The method of claim 1 further comprising equalizing the first bias voltage and the second bias voltage.
3. The method of claim 1 wherein the first bias voltage and the second bias voltage are an inverted pair.
4. The method of claim 1 further comprising:
filtering the accumulated phase offset and the reference offset;
comparing the filtered accumulated phase offset and the filter reference offset.
5. The method of claim 1 further comprising integrating the correctional signal.
6. The method of claim 1 wherein the n equals to 4 and the two adjacent output signals are separated by 90 degrees.
7. The method of claim 1 wherein the first phase signal is at phase 0 degree and the last phase signal is at phase 270 degrees.
8. The method of claim 1 further comprising applying the first bias voltage and the second bias voltage when generating the n output signals.
9. The method of claim 1 wherein the delay line comprises m delay modules arranged in series.
10. The method of claim 1 wherein the edge shape is substantially vertical.
11. The method of claim 1 wherein n is associated with a predetermined number of phases.
12. The method of claim 1 further comprising determining an overlap between the two adjacent output signals.
13. The method of claim 1 further comprising filtering the reference phase offset to extract DC information.
14. The method of claim 1 further comprising applying the first bias voltage and the second bias voltage to the delay line.
15. The method of claim 1 wherein the n output signals correspond to n phases.
16. A method for operating a receiver system, the method comprising:
receiving a reference clock signal;
performing phase interpolation on the reference clock signal to generate a corrected clock signal;
generating n output signals based on the corrected clock signal, the n output signals including a first phase signal and a last phase signal;
determining an accumulated phase offset using the first phase signal and the last phase signal;
determining a reference phase offset using two adjacent output signals of the n output signals;
generating a correctional signal using at least the accumulated phase offset and the reference phase offset;
generating a first bias voltage and a second bias voltage using at least the correction signal; and
generating a plurality of delayed signals using at least the corrected clock signal and the first bias voltage.
17. The method of claim 16 wherein the phase interpolation is performed using at least time recovery information.
18. A method for operating a delay-lock loop (DLL) system, the method comprising:
receiving a clock signal;
generating n output signals using a delay line and the clock signal, the n output signals including a first phase signal and a last phase signal;
determining an accumulated phase offset using the first phase signal and the last phase signal;
filtering the accumulated phase offset to provide a first filtered offset;
determining a reference phase offset using two adjacent output signals of the n output signals;
filtering the reference phase offset to provide a second filtered offset;
generating a correction signal using at least the first filtered offset and the second filtered offset; and
generating a first bias voltage and a second bias voltage using at least the correction signal.
19. The method of claim 18 further comprising integrating the correction signal.
20. The method of claim 18 further applying the first bias voltage and the second bias voltage to the delay line.