Method and system for a sampled loop filter in a phase locked loop (PLL)
Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.
1. A system, comprising:
a phase locked loop (PLL) for generating at least one clock signal, said PLL comprising:
a phase frequency detector;
a sampled loop filter comprising a plurality of capacitors and at least one switch, wherein a capacitor of said plurality of capacitors is coupled to ground from each terminal of said at least one switch;
a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter; and
a frequency divider,
wherein the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero.
2. The system of claim 1 , wherein said frequency divider is a fractional-N divider.
3. The system of claim 1 , wherein a second switch in said sampled loop filter has switching times that are non-overlapping with switching times of said at least one switch.
4. The system of claim 3 , comprising a capacitor of said plurality of capacitors is coupled to ground from each terminal of said second switch.
5. The system of claim 1 , wherein said sampled loop filter provides a filtered output voltage for said plurality of VCOs.
6. The system of claim 1 , wherein a multiplexer coupled to said plurality of VCOs feeds back an output of one of said plurality of VCOs to said frequency divider.
7. The system of claim 1 , wherein said at least one switch may be sub-sampled.
8. A method, comprising:
in a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, wherein a capacitor of said plurality of capacitors is coupled to ground from each terminal of said at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider:
generating at least one clock signal, wherein the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero.
9. The method of claim 8 , wherein said frequency divider is a fractional-N divider.
10. The method of claim 8 , wherein a second switch in said sampled loop filter has switching times that are non-overlapping with switching times of said at least one switch.
11. The method according to claim 10 , wherein a capacitor of said plurality of capacitors is coupled to ground from each terminal of said second switch.
12. The method of claim 8 , wherein said sampled loop filter provides a filtered output voltage for said plurality of VCOs.
13. The method of claim 8 , wherein a multiplexer coupled to said plurality of VCOs feeds back an output of one of said plurality of VCOs to said frequency divider.
14. The method of claim 8 , comprising sub-sampling said at least one switch.
15. A system, comprising:
a phase locked loop (PLL), said PLL comprising:
a phase frequency detector;
a sampled loop filter comprising a plurality of capacitors and at least one switch, wherein a capacitor of said plurality of capacitors is coupled to ground from each terminal of said at least one switch;
a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter; and
a frequency divider,
wherein said PLL is operable to :
sample an output signal from the phase frequency detector utilizing said at least one switch in said sampled loop filter when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero; and
generate a clock signal utilizing one of said plurality of VCOs that receives an output voltage from said sampled loop filter.
16. The system of claim 15 , wherein a second switch in said sampled loop filter has switching times that are non-overlapping with switching times of said at least one switch.
17. The system of claim 15 , wherein said frequency divider is a fractional-N divider.
18. A system, comprising:
a phase locked loop (PLL) for generating at least one clock signal, said PLL comprising:
a phase frequency detector;
a sampled loop filter comprising a plurality of capacitors and at least one switch;
a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter; and
a frequency divider,
wherein the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero and a second switch in said sampled loop filter has switching times that are non-overlapping with switching times of said at least one switch.
19. The system of claim 18 , wherein said frequency divider is a fractional-N divider.
20. The system of claim 18 , wherein a capacitor of said plurality of capacitors is coupled to ground from each terminal of said second switch.
21. The system of claim 18 , wherein said sampled loop filter provides a filtered output voltage for said plurality of VCOs.
22. The system of claim 18 , wherein a multiplexer coupled to said plurality of VCOs feeds back an output of one of said plurality of VCOs to said frequency divider.
23. The system of claim 18 , wherein said at least one switch may be sub-sampled.
24. A method, comprising:
in a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider:
generating at least one clock signal, wherein the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero and a second switch in said sampled loop filter has switching times that are non-overlapping with switching times of said at least one switch.
25. The method of claim 24 , wherein said frequency divider is a fractional-N divider.
26. The method according to claim 24 , wherein a capacitor of said plurality of capacitors is coupled to ground from each terminal of said second switch.
27. The method of claim 24 , wherein said sampled loop filter provides a filtered output voltage for said plurality of VCOs.
28. The method of claim 24 , wherein a multiplexer coupled to said plurality of VCOs feeds back an output of one of said plurality of VCOs to said frequency divider.
29. The method of claim 24 , comprising sub-sampling said at least one switch.
30. A system, comprising:
a phase locked loop (PLL), said PLL comprising:
a phase frequency detector;
a sampled loop filter comprising a plurality of capacitors and at least one switch, wherein a second switch in said sampled loop filter has switching times that are non-overlapping with switching times of said at least one switch;
a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter; and
a frequency divider,
wherein said PLL is operable to :
sample an output signal from the phase frequency detector utilizing said at least one switch in said sampled loop filter when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero; and
generate a clock signal utilizing one of said plurality of VCOs that receives an output voltage from said sampled loop filter.
31. The system of claim 30 , wherein said frequency divider is a fractional-N divider.