Method of manufacturing a P-channel power MOSFET
In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p + polysilicon gate electrode and a p + field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.
1. A method of manufacturing a double-gate-in-trench p-channel power MOSFET with reduced negative bias temperature instability, comprising the steps of:
(a) providing a p-type silicon-based semiconductor substrate having first and second principal surface sides;
(b) forming a p-type silicon epitaxial region over the first principal surface side of the p-type silicon-based semiconductor substrate, the p-type silicon epitaxial region constituting a drain region of the p-channel power MOSFET;
(c) forming an n-type well region in the p-type silicon epitaxial region, the n-type well region constituting a channel region of the p-channel MOSFET;
(d) forming a p-type impurity region in the n-type well region, the p-type impurity region constituting a source region of the p-channel power MOSFET;
(e) forming a pair of linear trenches in the p-type silicon epitaxial region, the pair of linear trenches extending through both of the n-type well region and the p-type impurity region;
(f) forming a linear contact groove in the n-type well region between the pair of linear trenches and extending through the p-type impurity region;
(g) forming an n-type contact region in the n-type well region between the pair of linear trenches and adjacent to a bottom portion of the linear contact groove, and
(h) providing a gate structure configured in accordance with an arrangement that has been predetermined to reduce negative bias temperature instability, said gate structure comprising, in each of the linear trenches:
an n-type polysilicon linear field plate electrode that extends from the p-type silicon epitaxial region into the n-type well region;
an n-type polysilicon linear gate electrode that extends from the p-type silicon epitaxial region, through the n-type well region and into the p-type impurity region, and is disposed over and along the n-type polysilicon linear field plate electrode; and
a gate insulating film formed between the n-type polysilicon linear gate electrode and the n-type well region.
2. A method according to claim 1 ,
wherein the second principal surface side of the silicon-based semiconductor substrate is provided with a metal drain electrode.
3. A method according to claim 2 ,
wherein the n-type polysilicon linear field plate electrode and the n-type polysilicon linear gate electrode are electrically coupled to each other.
4. A method according to claim 3 ,
wherein the n-type polysilicon linear field plate electrode and the n-type polysilicon linear gate electrode are coupled with each other outside each linear trench.
5. A method according to claim 4 ,
wherein the n-type polysilicon linear field plate electrode and the n-type polysilicon linear gate electrode are coupled with each other via a metal wiring line outside each linear trench.
6. A method according to claim 5 ,
wherein the p-channel power MOSFET is arranged for motor driving use.
7. A method according to claim 6 ,
wherein the p-channel power MOSFET is arranged for use as a low-threshold-voltage device.
8. A method according to claim 1 , wherein step (c) is performed after steps (e) and (h).
9. A method of manufacturing a double-gate-in-trench p-channel power MOSFET with reduced negative bias temperature instability, comprising the steps of:
(a) providing a p-type silicon-based semiconductor substrate having first and second principal surface sides;
(b) after step (a), forming a p-type silicon epitaxial region over the first principal surface side of the p-type silicon-based semiconductor substrate, the p-type silicon epitaxial region constituting a drain region of the p-channel power MOSFET;
(c) after step (b), forming a pair of linear trenches in the p-type silicon epitaxial region;
(d) after step (c), configuring a gate structure in accordance with an arrangement that has been predetermined to reduce negative bias temperature instability, the gate structure including an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode, and the step (d) including, in each of the linear trenches:
(d1) forming a first insulating film corresponding to a periphery of the n-type polysilicon linear field plate electrode over a lower portion of an inside surface of the trench;
(d2) after step (d1), forming the n-type polysilicon linear field plate electrode in the lower portion of the trench so as to be surrounded by the first insulating film;
(d3) after step (d2), forming a second insulating film corresponding to a periphery of the n-type polysilicon linear gate electrode over an upper portion of the inside surface of the trench; and
(d4) after step (d3), forming an n-type polysilicon linear gate electrode in the upper portion of the trench over and along an upper portion of the n-type polysilicon linear field plate electrode, so as to be surrounded by the second insulating film;
(e) after step (d), forming an n-type well region in the p-type silicon epitaxial region between the pair of linear trenches, the n-type well region constituting a channel region of the p-channel MOSFET;
(f) after step (e), forming a p-type impurity region in the n-type well region, the p-type impurity constituting a source region of the p-channel MOSFET;
(g) after step (f), forming a linear contact groove in the n-type well region between the pair of linear trenches and extending through the p-type impurity region;
(h) after step (g), forming an n-type contact region in the n-type well region between the pair of linear trenches and adjacent to a bottom portion of the linear contact groove.
10. A method according to claim 9 ,
wherein the second principal surface side of the silicon-based semiconductor substrate is provided with a metal drain electrode.
11. A method according to claim 10 ,
wherein the n-type polysilicon linear field plate electrode and the n-type polysilicon linear gate electrode are electrically coupled to each other.
12. A method according to claim 11 ,
wherein the n-type polysilicon linear field plate electrode and the n-type polysilicon linear gate electrode are coupled with each other outside each linear trench.
13. A method according to claim 12 ,
wherein the n-type polysilicon linear field plate electrode and the n-type polysilicon linear gate electrode are coupled with each other via a metal wiring line outside each linear trench.
14. A method according to claim 13 ,
wherein the p-channel power MOSFET is arranged for motor driving use.
15. A method according to claim 14 ,
wherein the p-channel power MOSFET is arranged for use as a low-threshold-voltage device.