Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
1. A semiconductor memory array comprising a plurality of single polysilicon floating gate semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said single polysilicon floating gate semiconductor memory cell comprising:
a substrate;
a floating body region exposed at a surface of said substrate and configured to store volatile memory;
a single polysilicon floating gate configured to store nonvolatile data;
an insulating region insulating said floating body region from said single polysilicon floating gate; and
first and second regions exposed at said surface at locations other than where said floating body region is exposed;
wherein said floating gate is configured to receive transfer of data stored by the floating body region.
2. The semiconductor memory array of claim 1 , wherein said first and second regions are asymmetric, wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface, and wherein said first area is unequal to said second area.
3. The semiconductor memory array of claim 1 , wherein one of said first and second regions at the surface has a higher coupling to said floating gate relative to coupling of the other of said first and second regions to said floating gate.
4. The semiconductor memory array of claim 1 , further comprising a buried layer at a bottom portion of the substrate, said buried layer having a conductivity type that is different from a conductivity type of said floating body region.
5. The semiconductor memory array of claim 4 wherein said floating body is bounded by said surface, said first and second regions and said buried layer.
6. The semiconductor memory array of claim 1 , further comprising insulating layers bounding side surfaces of said substrate.
7. The semiconductor memory array of claim 1 , further comprising a buried insulator layer buried in a bottom portion of said substrate.
8. The semiconductor memory array of claim 7 , wherein said floating body is bounded by said surface, said first and second regions and said buried insulator layer.
9. The semiconductor memory array of claim 1 , wherein said floating gate overlies an area of said floating body exposed at said surface, and wherein a gap is located between said area overlaid and one of said first and second regions.
10. The semiconductor memory array of claim 1 , further comprising a select gate positioned adjacent to said single polysilicon floating gate.
11. The semiconductor memory array of claim 4 , wherein said first and second regions are asymmetric, wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface, and wherein said first area is unequal to said second area.
12. The semiconductor memory array of claim 1 , wherein said select gate overlaps said floating gate.
13. A semiconductor memory array comprising a plurality of single polysilicon floating gate semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said single polysilicon floating gate semiconductor memory cell comprising:
a substrate;
a floating body region for storing data as volatile memory, and
a single polysilicon floating gate for storing data as non-volatile memory;
wherein said floating body region stores the data stored as volatile memory independently of said data stored as non-volatile memory, and said single polysilicon floating gate stores said data stored as non-volatile memory independently of said data stored as volatile memory.
14. The semiconductor memory array of claim 13 , wherein said floating body region has a first conductivity type and is bounded by a buried layer having a second conductivity type different from said first conductivity type.
15. The semiconductor memory array of claim 13 , wherein said floating body region is bounded a buried insulator.
16. The semiconductor memory array of claim 14 , wherein said first conductivity type is “p” type and said second conductivity type is “n” type.
17. The semiconductor memory array of claim 13 , further comprising insulating layers bounding side surfaces of said substrate.
18. The semiconductor memory array of claim 13 , wherein each said single polysilicon floating gate semiconductor memory cell is configured such that operations can be performed on said data stored as volatile memory regardless of a state of said data stored as non-volatile memory.
19. The semiconductor memory array of claim 18 , wherein said operations include read, write, hold, reset and shadow.
20. The semiconductor memory array of claim 13 , wherein each said single polysilicon floating gate semiconductor memory cell is configured such that operations can be performed on said data stored as non-volatile memory regardless of a state of said data stored as volatile memory.