Memory system storing 4-bit data in each memory cell and method of controlling thereof including soft bit information
View Patent ↗According to one embodiment, a memory system acquires HB information and SB1 information through SB4 information on each of four pages including LOWER, MIDDLE, UPPER, and HIGHER pages from a NAND memory 100 that includes QLCs each being capable of retaining a 4-bit value. An ECC circuit 260 of a memory controller 200 decodes the acquired HB information and SB1 to SB4 information on the four pages.
1. A memory system comprising:
a non-volatile memory that includes memory cells each being capable of retaining a 4-bit value;
a controller that controls a write and a read of data to and from the non-volatile memory; and
a decoder that decodes data read from the non-volatile memory, wherein
the controller acquires, when the total number of first read levels set for one of the memory cells with respect to first to fourth pages is P and the number of second read levels set for a higher side or a lower side of each of the first read levels is Q, information of S−1 pieces which is less than S pieces of information calculated using the following expression by 1 for acquiring information about the first to fourth pages from the one of the memory cells,
S =(the number of bits required to represent ( P+ 1) areas)+(the number of bits required to represent ( Q+ 1) areas),
one of the numbers of the first read levels set for the one of the memory cells with respect to the respective first to fourth pages is three, the numbers of the first read levels set for the one of the memory cells with respect to the respective residual pages are four, P is fifteen and Q is three, and
the decoder decodes the S−1 pieces of information acquired by the controller.
2. The memory system according to claim 1 , wherein the S−1 pieces of information are constructed from first information read out using the first read level and second to fifth information read out using the second read level.
3. The memory system according to claim 2 , wherein
the non-volatile memory includes a sequencer that controls a read from the memory cells, and
the sequencer
acquires respective pieces of the first information on the first to fourth pages by performing a first read from the memory cells four times, and
acquires the second information to the fifth information on each of the first to fourth pages by performing a second read from the memory cells four times with respect to each of the first to fourth pages.
4. The memory system according to claim 3 , wherein
the sequencer
acquires the first information on the first page by performing the first read of the first page using three different first read levels,
acquires the first information on the second page by performing the first read of the second page using four different first read levels,
acquires the first information on the third page by performing the first read of the third page using four different first read levels, and
acquires the first information on the fourth page by performing the first read of the fourth page using four different first read levels,
the fifteen first read levels in total are voltage values different from each other,
the controller acquires the second to fifth information on the first to fourth pages, respectively, by performing the second read using six second read levels that are set for each of the fifteen first read levels, and
the six second read levels set for each of the first read levels are read levels that are set with predetermined step sizes from a corresponding one of the first read levels.
5. The memory system according to claim 2 , wherein
the non-volatile memory includes a sequencer that controls a read from the memory cells, and
the sequencer acquires the first to fifth information on each of the first to fourth pages by performing first to fourth reads to the memory cells.
6. The memory system according to claim 5 , wherein
the first read levels include three different third read levels, four different fourth read levels, four different fifth read levels and four different sixth read levels, the third read levels, the fourth read levels, the fifth read levels and the sixth read levels being voltage values different from each other,
the sequencer
acquires the first to fifth information on the first page by performing the first read using the three different third read levels and six second read levels that are set for each of the third read levels,
acquires the first to fifth information on the second page by performing the second read using the four different fourth read levels and six second read levels that are set for each of the fourth read levels,
acquires the first to fifth information on the third page by performing the third read using the four different fifth read levels and six second read levels that are set for each of the fifth read levels, and
acquires the first to fifth information on the fourth page by performing the fourth read using the four different sixth read levels and six second read levels that are set for each of the sixth read levels,
the six second read levels that are set for each of the third read levels are read levels that are set with predetermined step sizes from a corresponding one of the third read levels,
the six second read levels that are set for each of the fourth read levels are read levels that are set with predetermined step sizes from a corresponding one of the fourth read levels,
the six second read levels that are set for each of the fifth read levels are read levels that are set with predetermined step sizes from a corresponding one of the fifth read levels, and
the six second read levels that are set for each of the sixth read levels are read levels that are set with predetermined step sizes from a corresponding one of the sixth read levels.
7. The memory system according to claim 6 , wherein
the sequencer
performs the first read using a first waveform that transitions from a lower read level to a higher read level among the three different third read levels and the six second read levels set for each of the third read levels,
performs the second read using a second waveform that transitions from a lower read level to a higher read level among the four different fourth read levels and the six second read levels set for each of the fourth read levels,
performs the third read using a third waveform that transitions from a lower read level to a higher read level among the four different fifth read levels and the six second read levels set for each of the fifth read levels, and
performs the fourth read using a fourth waveform that transitions from a lower read level to a higher read level among the four different sixth read levels and the six second read levels set for each of the sixth read levels.
8. The memory system according to claim 7 , wherein the first to fourth waveforms are waveforms increasing in a stepwise manner.
9. The memory system according to claim 7 , wherein the first to fourth waveforms are waveforms increasing in a slope manner.
10. The memory system according to claim 2 , wherein
the first page is a LOWER page,
the second page is a MIDDLE page,
the third page is an UPPER page,
the fourth page is a HIGHER page,
the first information is hard bit information, and
the second information to the fifth information are soft bit information, respectively.
11. A method of controlling a memory system comprising a non-volatile memory that includes memory cells each being capable of retaining a 4-bit value, a controller that control a write and a read of data to and from the non-volatile memory, and a decoder that decodes data read from the non-volatile memory, wherein
the controller acquires, when the total number of first read levels set for one of the memory cells with respect to first to fourth pages is P and the number of second read levels set for a higher side or a lower side of each of the first read levels is Q, information of S−1 pieces which is less than S pieces of information calculated using the following expression by 1 for acquiring information about the first to fourth pages from the one of the memory cells,
S =(the number of bits required to represent ( P+ 1) areas)+(the number of bits required to represent ( Q+ 1) areas),
one of the numbers of the first read levels set for the one of the memory cells with respect to the respective first to fourth pages is three, the numbers of the first read levels set for the one of the memory cells with respect to the respective residual pages are four, P is fifteen, and Q is three, and
the decoder decodes the S−1 pieces of information acquired by the controller.