Memory Device Interconnects and Method of Manufacture
A method of fabricating an integrated circuit memory device including forming a first and second inter-level dielectric layer, an anti-reflective coating layer, and a plurality of electrical connections is disclosed.
1 - 20 . (canceled)
21 . A method of fabricating a memory array comprising:
forming, through a first dielectric layer, a first plurality of electrical connections;
forming, on the first dielectric layer, second dielectric layer;
depositing, on the second dielectric layer, an anti-reflective coating layer;
forming, through the second dielectric layer and the anti-reflective coating layer, a second plurality of electrical connections.
22 . The method of claim 21 , wherein the first dielectric layer comprises silicon dioxide (SiO2) or polyimide.
23 . The method of claim 21 , further comprising forming the first plurality of electrical connections from a first metal layer.
24 . The method of claim 21 , further comprising forming the second plurality of electrical connections from a second metal layer.
25 . The method of claim 23 , wherein the first metal layer comprises tungsten, titanium, or titanium nitrate.
26 . The method of claim 24 , wherein the second metal layer comprises tungsten, titanium, or titanium nitrate.