Triple-pass execution using a retire queue having a functional unit to independently execute long latency instructions and dependent instructions
An execution pipeline architecture of a microprocessor employs a third-pass functional unit, for example, third-level of arithmetic logic unit (ALU) or third short-latency execution unit to execute instructions with reduced complexity and area cost of out-of-order execution. The third-pass functional unit allows instructions with long latency execution to be moved into a retire queue. The retire queue further includes the third functional unit (e.g., ALU), a reservation station and a graduate buffer. Data dependencies of dependent instructions in the retire queue is handled independently from the main pipeline.
1. A microprocessor including an extended pipeline stage comprising:
a main execution pipeline processing instructions and configured to forward long latency instructions to a retire queue, the main execution pipeline including an arithmetic logic unit (ALU), the long latency instructions being instructions taking more than one cycle to execute; and
the retire queue configured to store and execute the long latency instructions and third-pass instructions, wherein one or more of the third-pass instructions have data dependencies upon the long latency instructions, and wherein the third-pass instructions are determined to, when executed, not cause any exception events, the retire queue further comprising:
a graduate buffer configured to store the long latency instructions;
a reservation station configured to store the third-pass instructions and dependency indications of the third-pass instructions on the long latency instructions stored in the graduate buffer; and
a third-pass functional unit configured to receive result data of the long latency instructions and to execute the third-pass instructions using the result data, processing of the third-pass instructions being executed independently from the instructions in the main execution pipeline, wherein the third-pass functional unit comprises one or more additional ALUs separate from the main execution pipeline and the one or more additional ALUs execute the third-pass instructions.
2. The microprocessor of claim 1 , wherein the third-pass instructions include at least one of an arithmetic logic unit (ALU) instruction and a shift instruction.
3. The microprocessor of claim 1 , wherein the long latency instructions and the third-pass instructions are stored in separate queues.
4. The microprocessor of claim 1 , further comprising a data dependency matrix configured to forward data between a long latency instruction and a third-pass instruction.
5. The microprocessor of claim 1 , further comprising a data dependency matrix configured to forward data between third-pass instructions.
6. The microprocessor of claim 1 , wherein the long latency instructions are instructions that can cause a stall in the main execution pipeline.
7. The microprocessor of claim 1 , wherein the long-latency instructions include at least one of load/store instructions with cache misses, divide instructions, floating point instructions, and custom instructions with long latency.
8. The microprocessor of claim 1 , further comprising multiple queues with each of the multiple queues dedicated to a corresponding additional ALU.
9. The microprocessor of claim 1 , further comprising:
a register file that receives result data from the third-pass functional unit.
10. The microprocessor of claim 1 , wherein the microprocessor is a component of a computer system, the computer system comprising at least one of a memory, graphics display unit, or a storage unit.
11. A method comprising:
fetching an instruction from a main execution pipeline, the main execution pipeline includes an arithmetic logic unit (ALU);
determining whether the instruction is a long latency instruction, wherein a long latency instruction is an instruction that, when executed, causes a stall in the main execution pipeline;
forwarding, responsive to determining the instruction is a long latency instruction, the instruction to a graduate buffer of a retire queue, wherein the graduate buffer is configured to store the long latency instruction;
identifying a third-pass instruction in the main execution pipeline, the third-pass instruction depending only upon one or more instructions in the retire queue, wherein the third-pass instruction is determined to, when executed, not generate an exception;
forwarding the identified third-pass instruction to a reservation station of the retire queue, wherein the reservation station is configured to store the third-pass instructions and dependency indications of the third-pass instructions on long-latency instructions stored in the graduate buffer; and
executing the third-pass instruction in a third-pass functional unit of the retire queue, wherein the third-pass functional unit comprises one or more additional ALUs.
12. The method of claim 11 , further comprising:
storing the long-latency instruction and the third-pass instruction in separate queues within the retire queue.
13. The method of claim 11 , wherein the executing the third-pass instruction in the third-pass functional unit of the retire queue further comprises:
determining that the third-pass instruction has no data dependency; and
executing the third-pass instruction out-of-order.
14. The method of claim 11 , further comprising:
forwarding an output data of the third-pass functional unit to a data dependency matrix, the data dependency matrix configured to forward the output data between a long latency instruction and a third-pass instruction.
15. The method of claim 11 , further comprising:
forwarding an output data of the third pass functional unit to a data dependency matrix, the data dependency matrix configured to forward the output data between third-pass instructions.
16. The method of claim 11 , wherein the long latency instruction is an instruction that causes a stall in the main execution pipeline.
17. The method of claim 11 , wherein the long latency instruction includes at least one of load/store instructions with cache misses, divide instructions, floating point instructions, and custom instructions with long latency.
18. The method of claim 11 , wherein the main execution pipeline further comprises multiple queues with each of the multiple queues dedicated to a corresponding additional ALU.
19. The method of claim 11 , further comprising:
forwarding result data from the third-pass functional unit to a register file included in the main execution pipeline.
20. The method of claim 11 , wherein the microprocessor is a component of a computer system, the computer system comprising at least one of a memory, graphics display unit, and a storage unit.
21. The method of claim 11 , further comprising:
determining whether the instruction is a branch instruction, wherein the branch instruction is an instruction, that, when executed, changes the flow of execution by misprediction; and
responsive to determining the instruction is a branch instruction, executing the instruction in the main execution pipeline.