Superjunction semiconductor device

1. A superjunction semiconductor device, comprising:

a first semiconductor layer doped with a first conductivity type;

an active region formed on the first semiconductor layer, the active region including a drift layer; and

a termination region surrounding the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region,

the upper edge region including a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type, and

the lower edge region including a first pillar and a second pillar, the first pillar and the second pillar both being aligned along a direction perpendicular to a top surface of the first semiconductor layer, the first pillar having the first conductivity type and the second pillar having the second conductivity type.

2. The superjunction semiconductor device according to claim 1 ,

wherein the upper charge balance region is disposed on substantially an entire area of the termination region.

3. The superjunction semiconductor device according to claim 1 , wherein the drift layer includes a first portion having the first conductivity type and a second portion having the second conductivity type, which extend along a direction parallel to the top surface of the first semiconductor layer.

4. The superjunction semiconductor device according to claim 3 , wherein the first pillar and the second pillar, respectively, are connected to the first portion and the second portion of the drift layer.

5. The superjunction semiconductor device according to claim 4 , wherein the lower charge balance region is disposed on at least the first pillar.

6. The superjunction semiconductor device according to claim 4 , wherein the upper charge balance region vertically overlaps with at least the first pillar.

7. The superjunction semiconductor device according to claim 1 , wherein uppermost sidewalls of the first portion and the second portion of the drift layer are in contact with a sidewall of the upper charge balance region.

8. The superjunction semiconductor device according to claim 1 , wherein an interface between the upper charge balance region and the lower charge balance region is disposed to be spaced apart from a top surface of the upper charge balance region in a direction perpendicular to the top surface of the first semiconductor layer.

9. The superjunction semiconductor device according to claim 1 , wherein the lower charge balance region has a first impurity concentration, the second portion of the drift layer has a second impurity concentration, and the first impurity concentration is smaller than the second impurity concentration.

10. The superjunction semiconductor device according to claim 1 , wherein the lower and upper charge balance regions form a P-N junction.

11. The superjunction semiconductor device according to claim 1 , wherein the drift layer has a first height along a direction perpendicular to the top surface of the first semiconductor layer, the lower edge region has a second height along the direction perpendicular to the top surface of the first semiconductor layer, and the second height is about 70% to 98% of the first height.

12. The superjunction semiconductor device according to claim 1 , wherein the drift layer has a first height along a direction perpendicular to the top surface of the first semiconductor layer, the lower edge region has a second height along the direction perpendicular to the top surface of the first semiconductor layer, and the second height is about 85% to 95% of the first height.

13. A superjunction semiconductor device, comprising:

an active region; and

a termination region surrounding the active region,

wherein the active region includes:

a first semiconductor layer having N-type conductivity; and

a drift layer disposed on the first semiconductor layer,

wherein the termination region includes an upper edge region and a lower edge region, the upper edge region including:

a lower charge balance region disposed on one side of the drift layer, the lower charge balance region having P-type conductivity, and

an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having N-type conductivity; and

the lower edge region including:

a first pillar and a second pillar, the first pillar and the second pillar both being aligned along a direction perpendicular to a top surface of the first semiconductor layer, the first pillar having the N-type conductivity and the second pillar having the P-type conductivity.

14. The superjunction semiconductor device according to claim 13 , wherein the upper charge balance region is formed on substantially an entire area of the termination region, and

the lower charge balance region vertically overlaps with the upper charge balance region.

15. The superjunction semiconductor device according to claim 13 , wherein the drift layer includes a N type pillar and a P-type pillar, which extend along a direction parallel to a top surface of the first semiconductor layer.

16. The superjunction semiconductor device according to claim 15 , wherein the lower edge region is disposed under the upper charge balance region, on a side surface of the drift layer, and

the lower edge region includes a first N-type pillar and a first P-type pillar, which are respectively connected to the N-type pillar of the drift layer and the P-type pillar of the drift layer.

17. The superjunction semiconductor device according to claim 16 , wherein the lower edge region includes a second N-type pillar and a second P-type pillar, which are disposed on one side of the first N-type pillar and the first P-type pillar along a direction perpendicular to the top surface of the first semiconductor layer.

18. The superjunction semiconductor device according to claim 17 , wherein the lower charge balance region is disposed on the first N-type pillar, the second N-type pillar, the first P-type pillar, and the second P-type pillar.

19. The superjunction semiconductor device according to claim 18 , wherein the lower charge balance region includes a first region and a second region, which are located on the first P-type pillar, and the first region is located closer to the drift layer than the second region, and

a third impurity concentration of the first region is substantially equal to a fourth impurity concentration of the second region.

20. The superjunction semiconductor device according to claim 19 , wherein the lower charge balance region includes a third region and a fourth region, which are respectively located on the second P-type pillar, and the third region is located closer to the drift layer than the fourth region, and

a fifth impurity concentration of the third region is substantially equal to a sixth impurity concentration of the fourth region.

21. The superjunction semiconductor device according to claim 18 , wherein the lower charge balance region includes a first region and a second region, which are located on the first P-type pillar, and the first region is located closer to the drift layer than the second region, and

a third impurity concentration of the first region is greater than a fourth impurity concentration of the second region.

22. The superjunction semiconductor device according to claim 21 , wherein the lower charge balance region includes a third region and a fourth region, which are respectively located on the second P-type pillar, and the third region is located closer to the drift layer than the fourth region, and

a fifth impurity concentration of the third region is greater than a sixth impurity concentration of the fourth region.

23. The superjunction semiconductor device according to claim 22 , wherein the lower charge balance region includes a fifth region and a sixth region, and the fifth region is located closer to the drift layer than the sixth region, and

the fifth region has a first thickness along a direction perpendicular to the top surface of the first semiconductor layer, and the sixth region has a second thickness smaller than the first thickness along the direction perpendicular to the top surface of the first semiconductor layer.