DEEP PROCESSING UNIT (DPU) FOR IMPLEMENTING AN ARTIFICIAL NEURAL NETWORK (ANN)
The present invention relates to artificial neural network, for example, convolutional neural network. In particular, the present invention relates to how to implement and optimize a convolutional neural network based on an embedded FPGA. Specifically, it proposes a CPU+FPGA heterogeneous architecture to accelerate ANNs.
1 . A deep processing unit (DPU) for implementing an Artificial Neural Network (ANN), comprising:
a CPU, configured for scheduling a programmable logic module,
an external memory, configured for storing weights and instructions of the ANN and input data to be processed by said ANN;
a direct memory access (DMA), connected to external memory, directly configured by the CPU for communication between the external memory and the programmable logic module;
a programmable logic module, comprising:
a controller, configured for getting instructions from the external memory and scheduling operations of a computing complex on the basis of the instructions;
a computing complex, including a plurality of processing elements (PEs), configured for performing operations on the basis of the instructions, weights, and data;
an input buffer, configured for preparing the input data, weights and instructions for the computing complex;
an output buffer, configured for storing intermediate data and calculation results of the computing complex.
2 . The DPU of claim 1 , the PE further comprises:
a convolver complex, coupled to the input buffer to receive weights and input data, configured for performing convolutional operations of CONV layers and FC layers of the ANN;
adder tree, coupled to the convolver complex, configured for summing results of convolution operation;
non-linear (NL) module, coupled to the adder tree, configured for applying a non-linear function to the output of adder tree;
pooling module, coupled to the NL module, configured for performing max-pooling operation on the output of NL module, and providing its output to the output buffer.
3 . The DPU of claim 1 , the PE further comprises:
bias shift, coupled to the input buffer, configured for shifting weights of ANN between different numerical ranges and providing said shifted weights to the adder tree, wherein the weights are quantized fixed-point numbers;
data shift, coupled to the output buffer, configured for shifting data between different numerical ranges, wherein the data are quantized fixed-point numbers.
4 . The DPU of claim 2 , wherein the convolver complex has a plurality of convolvers, and said convolver is 2-dimension multiplier.
5 . The DPU of claim 1 , wherein the input buffer further comprises
weight buffer, for storing weights of the ANN;
line data buffer, for storing data and holding the data with delayers in order to reuse the data.
6 . The DPU of claim 1 , wherein the controller further comprising:
instruction decoding module, configured for decoding the instructions being input to the controller;
scheduling module, configured for scheduling the plurality of PEs on the basis of the decoded instructions.
7 . The DPU of claim 1 , wherein the controller further comprising:
interruption module, configured for sending interruption signal to the CPU, and said CPU access DMA with writing or reading operation based on the interruption signal.
8 . The DPU of claim 1 , wherein the controller further comprising:
instruction granularity transforming module, configured for transforming coarse-granularity instruction into fine-granularity instructions based on the number of PE in said computing complex.
9 . The DPU of claim 1 , wherein the external memory is configured to store instructions for tiling the input data by factors Tr, Tc in row and column.
10 . The DPU of claim 9 , wherein the line data buffer is configured to store the tiled data.
11 . The DPU of claim 9 , wherein the external memory is configured to store tiled input data in a segmented manner based on the factors Tr, Tc.
12 . The DPU of claim 1 , wherein CPU is further configured to implement SOFTMAX function of the ANN.
13 . The DPU of claim 1 , wherein the CPU and the programmable logic module are implemented in one System-On-a-Chip.
14 . The DPU of claim 13 , wherein the external memory is implemented on a separate chip.
15 . The DPU of claim 1 , wherein the DMA communicates data with the input buffer and the output buffer via FIFO.
16 . The DPU of claim 1 , wherein the DMA communicates instructions with the controller via FIFO.
17 . The DPU of claim 1 , further comprising: data & instruction bus, configured for communication between CPU, the external memory and a programmable logic module.