Electronic timepiece
An electronic timepiece includes a first switch connected to a signal line, a second switch, and a one-shot pulse signal generation circuit. The first switch is inserted into the signal line. One end of the second switch is connected to the signal line at a rear stage of the first switch, and the other end of the second switch is connected to a power source. The one-shot pulse signal generation circuit generates a one-shot pulse signal by using a reference clock signal, and the second switch is controlled by the one-shot pulse signal. The timepiece device can reduce currents flowing in a pull-down resistor or a pull-up resistor when a crown switch is turned on.
1. An electronic timepiece comprising:
a first switch that is connected to a signal line;
a second switch; and
a one-shot pulse signal generation circuit,
wherein the first switch is inserted into the signal line,
wherein one end of the second switch is connected to the signal line at a rear stage of the first switch,
wherein the other end of the second switch is connected to a power source,
wherein the one-shot pulse signal generation circuit generates a one-shot pulse signal by using a reference clock signal,
wherein the second switch is controlled by the one-shot pulse signal,
wherein the one-shot pulse signal generation circuit includes a first inverter, a second inverter, a capacitor, and a NAND gate,
wherein the reference clock signal is input to an input terminal of the first inverter, and an input terminal of the second inverter and one input terminal of the NAND gate are connected to an output terminal of the first inverter,
wherein one end of the capacitor and the other input terminal of the NAND gate are connected to an output terminal of the second inverter,
wherein the other end of the capacitor is connected to a reference potential, and
wherein based on an output signal of the NAND gate, the one-shot pulse signal generation circuit generates a high level signal having a period shorter than a period while the reference clock signal is in a high level.
2. The electronic timepiece according to claim 1 , further comprising:
an oscillator circuit that generates an oscillation signal having a predetermined frequency;
a frequency divider circuit that frequency divides the oscillation signal; and
a clocking unit that clocks time based on a frequency-divided signal from the frequency divider circuit,
wherein the reference clock signal is a frequency-divided signal from the frequency divider circuit different from the frequency-divided signal used by the clocking unit to clock time, and
wherein the first switch selects a connection state and a disconnection state by operating a crown.
3. The electronic timepiece according to claim 1
wherein the capacitor includes a gate oxide film,
wherein a transistor configuring the second inverter delays falling of the reference clock signal by charging and discharging the capacitor, and
wherein a pulse width during a period while the one-shot pulse signal is in a high level is determined by the capacitance of the capacitor and driving ability of the transistor configuring the second inverter.
4. The electronic timepiece according to claim 1 ,
wherein the second switch is used as a first pull-down resistor so as to control a function of the first pull-down resistor in accordance with the one-shot pulse signal.
5. The electronic timepiece according to claim 4 ,
wherein a second pull-down resistor is inserted between the signal line and the power source so as to control a function of the second pull-down resistor in accordance with an output level and a reset signal of the signal line.
6. The electronic timepiece according to claim 5 ,
wherein a third switch for connecting the signal line and the reference potential is inserted between the signal line and the reference potential so as to operate the third switch with the second switch in a complementary manner.
7. The electronic timepiece according to claim 1 ,
wherein a first pull-down resistor is inserted between the signal line and the second switch so as to control a function of the first pull-down resistor in accordance with the one-shot pulse signal.
8. An electronic timepiece comprising:
a first switch that is connected to a signal line;
a second switch; and
a one-shot pulse signal generation circuit,
wherein the first switch is inserted into the signal line,
wherein one end of the second switch is connected to the signal line at a rear stage of the first switch,
wherein the other end of the second switch is connected to a reference potential,
wherein the one-shot pulse signal generation circuit generates a one-shot pulse signal by using a reference clock signal,
wherein the second switch is controlled by the one-shot pulse signal,
wherein the one-shot pulse signal generation circuit includes a first inverter, a second inverter, a capacitor, and a NOR gate,
wherein the reference clock signal is input to an input terminal of the first inverter, and an input terminal of the second inverter and one input terminal of the NOR gate are connected to an output terminal of the first inverter,
wherein one end of the capacitor and the other input terminal of the NOR gate are connected to an output terminal of the second inverter,
wherein the other end of the capacitor is connected to a reference potential, and
wherein based on an output signal of the NOR rate, the one-shot pulse signal generation circuit generates a low level signal having a period shorter than a period while the reference clock signal is in a low level.
9. The electronic timepiece according to claim 8 , further comprising:
an oscillator circuit; that generates an oscillation signal having a predetermined trequency;
a frequency divider circuit that frequency divides the oscillation signal; and
a clocking unit that clocks time based on a frequency-divided signal from the frequency divider circuit,
wherein the reference clock signal is is a frequency-divided signal from the frequency divider circuit different from the frequency-divided signal used by the clocking unit to clock time, and
wherein the first switch selects a connection state and a disconnection state by operating a crown.
10. The electronic timepiece according to claim 8 ,
wherein the capacitor includes a gate oxide film,
wherein a transistor configuring the second inverter delays rising of the reference clock signal by charging and discharging the capacitor, and
wherein a pulse width during a period while the one-shot pulse signal is in a low level is determined by the capacitance of the capacitor and driving ability of the Lransistor configuring the second inverter.
11. The electronic timepiece according to claim 8 ,
wherein the second switch is used as a first pull-up resistor so as to control a function of the first pull-up resistor in accordance with the one-shot pulse signal.
12. The electronic timepiece according to claim 11 ,
wherein a second pull-up resistor is inserted between the signal line and the reference potential so as to control a function of the second pull-up resistor in accordance with an output level and a reset signal of the signal line.
13. The electronic timepiece according to claim 12 ,
wherein a third switch for connecting the signal line and the power source is inserted between the signal line and the power source so as to operate the third switch with the second switch in a complementary manner.