LDMOS transistor and method of forming the LDMOS transistor with improved RDS*CGD
The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.
1. A transistor, comprising:
a semiconductor substrate having a top surface;
a gate positioned above the top surface;
a first drain drift region positioned near the top surface and extending partially under the gate;
a first back gate region staggering with the first drain drift region under the gate;
a second drain drift region positioned directly under the first drain drift region and staggering with the first back gate region under the gate; and
a second back gate region positioned directly under the first back gate region and the second drain drift region,
a first drain dopant concentration peak (DCP) between the top surface and the first drain drift region, the first drain DCP extending partially under the gate;
a first back gate DCP between the top surface and the first back gate region, the first back gate DCP extending partially under the first drain DCP;
a second drain DCP between the first drain drift region and the second drain drift region, the second drain DCP extending partially under the first backgate DCP;
a second back gate DCP between the first back gate region and the second back gate region, the second back gate DCP extending partially under the second drain DCP; and
a third back gate DCP below the second back gate region, the third back gate DCP extending under and across the second drain DCP.
2. The transistor of claim 1 , further comprising: a top drain drift region between the top surface and the first drain drift region; and a top back gate region between the top surface and the first back gate region.
3. The transistor of claim 1 , further comprising:
a source region above the first back gate region and free from overlapping the gate; and
a surface region adjacent to the source region and partially under the gate, the surface region having a higher doping concentration than the first drain drift region and the second drain drift region.
4. The transistor of claim 1 , further comprising:
a drain region above the first drain drift region and free from overlapping the gate; and
an isolation structure laterally surrounding the drain region and having a greater depth than the drain region.
5. A transistor, comprising:
a substrate having a top surface;
a gate positioned above the top surface;
a p-doped region in the substrate, the p-doped region including a p-type dopant concentration peak (DCP) extending partially under the gate; and
an n-doped region in the substrate, the n-doped region including:
a first n-type DCP extending partially under the gate and partially and immediately above the p-type DCP; and
a second n-type DCP below the first n-type DCP, the second n-type DCP extending partially and directly under the p-type DCP,
wherein the p-doped region includes:
a top back gate section below the top surface and extending partially under the gate, a portion of the n-doped region overlapping a portion of the top back gate section; and
a middle back gate section interfacing the top back gate section along the p-type DCP, a groove in the middle back gate section being protruded by the second n-type DCP.
6. The transistor of claim 5 , wherein the p-doped region includes:
a second p-type DCP below the p-type DCP, the second p-type DCP extending partially under the second n-type DCP.
7. The transistor of claim 5 , wherein the p-doped region includes:
a second p-type DCP below the p-type DCP, the second p-type DCP extending under and across the second n-type DCP.
8. The transistor of claim 5 , further comprising:
a source region within the p-doped region and above the p-type DCP, the source region does not extend directly under the gate; and
a surface region adjacent to the source region and partially under the gate, the surface region having a higher doping concentration than the n-doped region.
9. The transistor of claim 5 , further comprising:
a drain region within the n-doped region and above the first n-type DCP, the drain region does not extend under the gate; and
an isolation structure laterally surrounding the drain region and having a greater depth than the drain region.
10. The transistor of claim 5 , wherein the n-doped region includes:
a top drain drift section below the top surface and extending partially under the gate;
a middle drain drift section interfacing the top drain drift section along the first n-type DCP, a groove in the middle drain drift section being protruded by the p-type DCP; and
a bottom drain drift section interfacing the middle drain drift section along the second n-type DCP, a portion of the bottom drain drift section overlapping a portion of the p-doped region.
11. The transistor of claim 5 , wherein the n-doped region includes:
a top drain drift section below the top surface and extending partially under the gate;
a middle drain drift section interfacing the top drain drift section along the first n-type DCP, a portion of the middle drain drift section overlapping a portion of the p-doped region adjacent the p-type DCP.
12. The transistor of claim 5 , wherein the n-doped region includes:
a top drain drift section below the top surface and extending partially under the gate;
a middle drain drift section interfacing the top drain drift section along the first n-type DCP, a first portion of the middle drain drift section overlapping a portion of the p-doped region adjacent the p-type DCP and a second portion of the middle drain drift section under lapping a portion of the p-doped region adjacent the p-type DCP.
13. The transistor of claim 5 , wherein a portion of the n-doped region adjacent the first n-type DCP overlaps a portion of the p-doped region adjacent a bottom portion of the middle gate section.
14. An integrated circuit, comprising:
a substrate having a top surface;
transistors, each including:
a gate positioned above the top surface;
a p-doped region in the substrate, the p-doped region including a p-type dopant concentration peak (DCP) extending partially under the gate; and
an n-doped region in the substrate, the n-doped region including:
a first n-type DCP extending partially under the gate and partially and immediately above the p-type DCP; and
a second n-type DCP below the first n-type DCP, the second n-type DCP extending partially and immediately under the p-type DCP,
wherein the p-doped region includes:
a top back gate section below the top surface and extending partially under the gate, a portion of the n-doped region overlapping a portion of the top back gate section; and
a middle back gate section interfacing the top back gate section along the p-type DCP, a groove in the middle back gate section being protruded by the second n-type DCP.
15. The integrated circuit of claim 14 , further comprising:
a source region within the p-doped region and above the p-type DCP, the source region does not extend directly under the gate; and
a surface region adjacent to the source region and partially under the gate, the surface region having a higher doping concentration than the n-doped region.
16. The integrated circuit of claim 14 , further comprising:
a drain region within the n-doped region and above the first n-type DCP, the drain region does not extend under the gate; and
an isolation structure laterally surrounding the drain region and having a greater depth than the drain region.
17. The integrated circuit of claim 14 , wherein the n-doped region includes:
a top drain drift section below the top surface and extending partially under the gate;
a middle drain drift section interfacing the top drain drift section along the first n-type DCP, a groove in the middle drain drift section being protruded by the p-type DCP; and
a bottom drain drift section interfacing the middle drain drift section along the second n-type DCP, a portion of the bottom drain drift section overlapping a portion of the p-doped region.
18. The transistor of claim 14 , wherein the n-doped region includes:
a top drain drift section below the top surface and extending partially under the gate;
a middle drain drift section interfacing the top drain drift section along the first n-type DCP, a portion of the middle drain drift section overlapping a portion of the p-doped region adjacent the p-type DCP.
19. The transistor of claim 14 , wherein the n-doped region includes:
a top drain drift section below the top surface and extending partially under the gate;
a middle drain drift section interfacing the top drain drift section along the first n-type DCP, a first portion of the middle drain drift section overlapping a portion of the p-doped region adjacent the p-type DCP and a second portion of the middle drain drift section underlapping a portion of the p-doped region adjacent the p-type DCP.
20. The transistor of claim 14 , wherein a portion of the n-doped region adjacent the first n-type DCP overlaps a portion of the p-doped region adjacent a bottom portion of the middle gate section.
21. An integrated circuit, comprising:
a substrate having a top surface; and
transistors, each including:
a gate positioned above the top surface;
a p-doped region in the substrate, the p-doped region including a p-type dopant concentration peak (DCP) extending partially under the gate;
an n-doped region in the substrate, the n-doped region including:
a first n-type DCP extending partially under the gate and partially and immediately above the p-type DCP; and
a second n-type DCP below the first n-type DCP, the second n-type DCP extending partially and immediately under the p-type DCP;
a second p-type DCP below the p-type DCP, the second p-type DCP extending partially under the second n-type DCP; and
a third p-type DCP below the second p-type DCP, the third p-type DCP extending under and across the second n-type DCP.