Device for generating a voltage reference comprising a non-volatile memory cell
A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.
1. A device for generating a reference voltage, the device comprising:
a first non-volatile memory cell comprising a control-gate transistor and a reading transistor; and
a second equivalent memory cell;
wherein the control-gate transistor comprises a gate terminal, a body, a first conduction terminal, and a second conduction terminal, the first conduction terminal and the second conduction terminal being connected together to form a control-gate terminal; and
wherein the reading transistor comprises a gate terminal connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal;
wherein a source terminal of the first non-volatile memory cell and a source terminal of the second equivalent memory cell are connected together; and
wherein the device is configured so that the reference voltage is acquired on the floating-gate terminal and is determined by conditions of supply of conduction terminals of the first non-volatile memory cell and the second equivalent memory cell.
2. The device according to claim 1 , wherein the second equivalent memory cell includes a reading transistor that has a control-gate terminal connected to floating-gate terminal.
3. The device according to claim 1 , wherein the second equivalent memory cell comprises a non-volatile memory cell comprising a control-gate transistor and a reading transistor and defining a second floating-gate terminal.
4. The device according to claim 1 , wherein, in the first non-volatile memory cell, an area of the control-gate transistor is larger than an area of the reading transistor.
5. The device according to claim 4 , wherein the area of the control-gate transistor and the area of the reading transistor are in a ratio 6:1.
6. The device according to claim 1 , wherein, in the first non-volatile memory cell, an area of the control-gate transistor is smaller than an area of the reading transistor.
7. The device according to claim 6 , wherein the area of the control-gate transistor and the area of the reading transistor are in a ratio 1:6.
8. The device according to claim 1 , wherein the control-gate transistor and reading transistor comprise NMOS transistors.
9. The device according to claim 1 , wherein the control-gate transistor and reading transistor comprise PMOS transistors.
10. A system comprising an operational amplifier and the device for generating a reference voltage according to claim 1 , wherein the device for generating a reference voltage is inserted as a differential pair in the operational amplifier, wherein the control-gate terminal of the first non-volatile memory cell is connected on an inverting branch of the operational amplifier and a control-gate terminal of the second equivalent memory cell is connected on a non-inverting branch of the operational amplifier.
11. A device comprising:
a first control-gate transistor comprising a gate terminal, a body, a first conduction terminal, and a second conduction terminal, the first conduction terminal and the second conduction terminal being connected together to form a first control-gate terminal;
a first reading transistor comprising a gate terminal connected to the gate terminal of the first control-gate transistor to form a first floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal, the gate terminal of the first reading transistor connected to the gate terminal of the first control-gate transistor to form a first floating-gate terminal;
a second control-gate transistor comprising a gate terminal, a body, a fifth conduction terminal, and a sixth conduction terminal, the fifth conduction terminal and the sixth conduction terminal being connected together to form a second control-gate terminal; and
a second reading transistor comprising a gate terminal, a body, a seventh conduction terminal and an eighth conduction terminal, the gate terminal of the second reading transistor connected to the gate terminal of the second control-gate transistor to form a floating-gate terminal, wherein the fourth conduction terminal and the eighth conduction terminal are connected together.
12. The device according to claim 11 , wherein the device is configured so that a reference voltage is acquired on the first floating-gate terminal and is determined by conditions of supply of the first control-gate terminal, the second control-gate terminal, the third conduction terminal, the fourth conduction terminal, the seventh conduction terminal, and the eighth conduction terminal.
13. The device according to claim 11 , wherein the device comprises a differential pair in an operational amplifier.
14. The device according to claim 13 , wherein the first control-gate terminal is connected on an inverting branch of the operational amplifier and the second control-gate terminal is connected on a non-inverting branch of the operational amplifier.
15. The device according to claim 11 , wherein the first control-gate transistor has an area that is larger than an area of the first reading transistor.
16. The device according to claim 11 , wherein the first control-gate transistor has an area that is smaller than an area of the first reading transistor.
17. A device for generating a reference voltage, the device comprising:
a first non-volatile memory cell comprising a first control-gate transistor and a first reading transistor; and
a second non-volatile memory cell comprising a second control-gate transistor and a second reading transistor;
wherein the first control-gate transistor comprises a gate terminal, a body, a drain terminal, and a source terminal, the drain terminal and the source terminal being connected together to form a first control-gate terminal;
wherein the first reading transistor comprises a gate terminal, a body, a drain terminal, and a source terminal, the gate terminal of the first reading transistor being connected to the gate terminal of the first control-gate transistor to form a first floating-gate terminal;
wherein the second control-gate transistor comprises a gate terminal, a body, a drain terminal, and a source terminal, the drain terminal and the source terminal being connected together to form a second control-gate terminal;
wherein the second reading transistor comprises a gate terminal, a body, a drain terminal, and a source terminal, the gate terminal of the second reading transistor being connected to the gate terminal of the second control-gate transistor to form a second floating-gate terminal; and
wherein the source terminal of the first reading transistor and the source terminal of the second reading transistor are connected together.
18. The device according to claim 17 , wherein the device is configured so that a reference voltage is acquired on the first floating-gate terminal and is determined by conditions of supply of conduction terminals of the first non-volatile memory cell and the second non-volatile memory cell.
19. The device according to claim 17 , wherein an area of the first control-gate transistor is at least six times larger than an area of the first reading transistor.
20. The device according to claim 17 , wherein an area of the first control-gate transistor is at least six times smaller than an area of the first reading transistor.