IP Library Granted Patent US 10,262,962
Granted Patent B2
US 10,262,962 · App. 15/244,699 · Granted Apr 16, 2019

Semiconductor device

Inventor: Yoshihiro Monma (Kanagawa, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L24/09H01L21/56H01L22/32H01L23/544H01L24/49H01L24/85H01L25/0657H01L24/48H01L2224/04042H01L2224/06153H01L2224/06155H01L2224/48145H01L2224/48247H01L2225/06562H01L2225/06565H01L2225/1052H01L2924/00014
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Quick Facts
Patent No.
US 10,262,962
App. No.
15/244,699
Granted
Apr 16, 2019
Kind
B2
Abstract

A semiconductor device includes a terminal, a first semiconductor chip, a second semiconductor chip located on the first semiconductor chip, a first pad located on the first semiconductor chip and electrically disconnected from a semiconductor circuit of the first semiconductor chip, a second pad located on the second semiconductor chip and electrically connected to a semiconductor circuit of the second semiconductor chip, a first wire electrically connecting the first terminal to the first pad, and a second wire electrically connecting the first pad to the second pad.

Claims (46)

1. A semiconductor device comprising:

a first terminal;

a second terminal;

a first semiconductor chip on a first substrate, the first substrate having a scribe area thereon around the first semiconductor chip;

a second semiconductor chip on a second substrate, the second substrate being on the first semiconductor chip and having a scribe area thereon around the second semiconductor chip;

a first pad located in the scribe area of the first substrate and not on the first semiconductor chip, and electrically disconnected from a semiconductor circuit of the first semiconductor chip;

a second pad located on the second semiconductor chip and electrically connected with a semiconductor circuit of the second semiconductor chip;

a third pad located on the first semiconductor chip, and electrically connected with the semiconductor circuit of the first semiconductor chip;

a fourth pad located in the scribe area of the second substrate and not on the second semiconductor chip, and electrically disconnected from the semiconductor circuit of the second semiconductor chip;

a first wire electrically connecting the first terminal to the first pad;

a second wire electrically connecting the first pad to the fourth pad;

a third wire electrically connecting the second terminal to the third pad; and

a fourth wire electrically connecting the third pad to the second pad.

2. The device according to claim 1 ,

wherein the first pad is located between the first terminal and the third pad.

3. The device according to claim 1 , wherein the fourth pad is located between the second terminal and the second pad.

4. The device according to claim 1 , wherein

a chip enable signal is transferred from the first terminal to a fifth pad electrically connected to a semiconductor circuit of a third semiconductor chip through the first wire, the first pad, the second wire, and the fourth pad.

5. The device of claim 1 , wherein the first and second semiconductor chips are rectangular in shape and have a long edge and a short edge,

the first pad located on the first substrate is located adjacent to the short edge of the first semiconductor chip, and

the second pad located on the second semiconductor chip is located adjacent to the long edge of the second semiconductor chip.

6. The device of claim 5 , wherein the second substrate extends outwardly from an edge of the first substrate adjacent to the long edge of the first semiconductor chip.

7. The device according to claim 1 , wherein the first pad is closer to an edge of the first substrate than the third pad, and the fourth pad is closer to an edge of the second substrate than the second pad.

8. A semiconductor device comprising:

a first terminal;

a second terminal;

a first semiconductor chip on a first substrate, the first substrate having a scribe area thereon around the first semiconductor chip;

a second semiconductor chip on a second substrate, the second substrate being on the first semiconductor chip and having a scribe area thereon around the second semiconductor chip;

a first pad located in the scribe area of the first substrate and not on the first semiconductor chip, and electrically connected to a test element;

a second pad located on the second semiconductor chip and electrically connected to a semiconductor circuit of the second semiconductor chip;

a third pad located on the first semiconductor chip, and electrically connected with the semiconductor circuit of the first semiconductor chip;

a fourth pad located in the scribe area of the second substrate and not on the second semiconductor chip, and electrically disconnected from the semiconductor circuit of the second semiconductor chip;

a first wire electrically connecting the first terminal to the first pad;

a second wire electrically connecting the first pad to the fourth pad;

a third wire electrically connecting the second terminal to the third pad; and

a fourth wire electrically connecting the third pad to the second pad.

9. The device according to claim 8 ,

wherein the first pad is located between the first terminal and the third pad.

10. The device according to claim 8 , wherein the fourth pad is located between the second terminal and the second pad.

11. The device according to claim 8 , wherein

a chip enable signal is transferred from the first terminal to a fifth pad electrically connected to a semiconductor circuit of a third semiconductor chip through the first wire, the first pad, the second wire, and the fourth pad.

12. The device of claim 8 , wherein the first and second semiconductor chips are rectangular in shape and have a long edge and a short edge,

the first pad located on the first substrate is located adjacent to the short edge of the first semiconductor chip, and

the second pad located on the second semiconductor chip is located adjacent to the long edge of the second substrate.

13. The device of claim 12 , wherein the second substrate extends outwardly from an edge of the first substrate adjacent to the long edge of the first semiconductor chip.

14. The device according to claim 8 , wherein the first pad is closer to an edge of the first substrate than the third pad, and the fourth pad is closer to an edge of the second substrate than the second pad.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2016
From: MONMA, YOSHIHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 040199/0365 →
Priority Claims (1)
JP 2015-173747 · Sep 3, 2015 · national
Continuity (1)
Related Publication 20170069588A1 · Mar 9, 2017
Cited By (1)
US 12,381,184