Semiconductor storage device with voltage generator which generates voltages and currents for read and write operations
According to one embodiment, a semiconductor storage device includes: a memory cell including a variable resistance element; a bit line coupled to the memory cell; and a first circuit applying a first voltage to the bit line in a write operation for the memory cell. When a temperature of the variable resistance element is lower than or equal to a first temperature, a temperature coefficient of the first voltage is 0. When the temperature of the variable resistance element is higher than the first temperature, the temperature coefficient of the first voltage is negative.
1. A semiconductor storage device comprising:
a memory cell including a variable resistance element;
a bit line coupled to the memory cell; and
a first circuit configured to apply a first voltage to the bit line in a write operation for the memory cell,
wherein:
when a temperature of the variable resistance element is lower than or equal to a first temperature value, a temperature coefficient of the first voltage is 0, and
when the temperature of the variable resistance element is higher than the first temperature value, the temperature coefficient of the first voltage is negative.
2. The device according to claim 1 , wherein the first circuit includes:
a first voltage generator configured to generate a second voltage, a temperature coefficient of the second voltage being 0; and
a second voltage generator configured to generate a third voltage, a temperature coefficient of the third voltage being negative,
wherein:
the first circuit is configured to apply a lower one of the second voltage and the third voltage as the first voltage in the write operation, and
the second voltage is equal to the third voltage when the temperature of the variable resistance element is at the first temperature value.
3. The device according to claim 1 , wherein the first voltage is applied to the memory cell when a state of the variable resistance element is changed from a high resistance state to a low resistance state.
4. The device according to claim 1 , wherein the variable resistance element is an interfacial phase change memory element (iPCM element) or a super lattice phase-change element.
5. The device according to claim 2 , wherein:
the first voltage generator includes a first bandgap reference (BGR) circuit configured to generate the second voltage, and
the second voltage generator includes a second BGR circuit configured to generate the third voltage.
6. The device according to claim 2 , wherein:
the first circuit further includes a voltage selection circuit configured to select the lower one of the second voltage and the third voltage,
the voltage selection circuit includes:
a first transistor of a first conductivity type in which a power-supply voltage is applied to a source;
a second transistor of the first conductivity type in which a source is coupled to a drain of the first transistor and a drain is coupled to a first interconnect;
a first operational amplifier configured to compare the second voltage with a voltage of the first interconnect, and apply a voltage corresponding to a comparison result by the first operational amplifier to a gate of the first transistor;
a second operational amplifier configured to compare the third voltage with the voltage of the first interconnect, and apply a voltage corresponding to a comparison result by the second operational amplifier to a gate of the second transistor; and
a first resistance element coupled between the first interconnect and a ground node, and
the first circuit is configured to output the voltage of the first interconnect as the first voltage.
7. The device according to claim 2 , wherein:
the first circuit includes a voltage selection circuit configured to select the lower one of the second voltage and the third voltage,
the voltage selection circuit includes:
a first transistor of a first conductivity type in which a drain is coupled to a first interconnect and a source is applied with a ground voltage;
a second transistor of the first conductivity type in which a drain is coupled to the first interconnect and a source is applied with the ground voltage;
a first operational amplifier configured to compare the second voltage with a voltage of the first interconnect and apply a voltage corresponding to a comparison result by the first operational amplifier to a gate of the first transistor;
a second operational amplifier configured to compare the third voltage with the voltage of the first interconnect and apply a voltage corresponding to a comparison result by the second operational amplifier to a gate of the second transistor;
a first resistance element coupled between the first interconnect and a power supply node, and
the first circuit is configured to output the voltage of the first interconnect as the first voltage.
8. The device according to claim 2 , wherein the second voltage generator includes:
a first BGR circuit configured to generate a first current, a temperature coefficient of the first current being 0; and
a second BGR circuit configured to generate a second current, a temperature coefficient of the second current being negative, and
wherein the second voltage generator is configured to generate the third voltage based on a sum of the first current and the second current.
9. The device according to claim 5 , wherein the first BGR circuit includes:
a first transistor of a first conductivity type in which a power-supply voltage is applied to a source, and a drain is coupled to a first interconnect;
a second transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to a second interconnect;
a third transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to a third interconnect;
a first operational amplifier configured to compare a voltage of the first interconnect with a voltage of the second interconnect, and apply a fourth voltage corresponding to a comparison result by the first operational amplifier to gates of the first to third transistors;
a first diode in which an anode is coupled to the first interconnect, and a cathode is coupled to a ground node;
N (N is an integer greater than or equal to 2) second diodes in which cathodes are coupled to the ground node and anodes are coupled to each other;
a first resistance element coupled between the first interconnect and the ground node;
a second resistance element coupled between the second interconnect and the ground node;
a third resistance element coupled between the third interconnect and the ground node; and
a fourth resistance element coupled between the second interconnect and the anodes of the N second diodes, and
wherein the first BGR circuit is configured to output a voltage of the third interconnect as the second voltage.
10. The device according to claim 9 , wherein, when a temperature characteristic value of a built-in potential of the second diode is −2[mV/° C.],
a resistance value of the first resistance element is R 1 , and
a resistance value of the fourth resistance element is R 3 ,
a following relationship is established:
( R 1/ R 3)·( k/q )·ln N= 2[mV],
wherein k is a Boltzmann constant and q is a charge amount of electrons.
11. The device according to claim 9 , wherein the second BGR circuit includes:
a fourth transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to fourth interconnect;
a fifth transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to fifth interconnect;
a sixth transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to sixth interconnect;
a second operational amplifier configured to compare a voltage of the fourth interconnect with a voltage of the fifth interconnect, and apply a fifth voltage corresponding to a comparison result by the second operational amplifier to gates of the fourth to sixth transistors;
a third diode in which an anode is coupled to the fourth interconnect and a cathode is coupled to the ground node;
M (M is an integer greater than or equal to 2) fourth diodes in which cathodes are coupled to the ground node and anodes are coupled to each other;
a fifth resistance element coupled between the fourth interconnect and the ground node;
a sixth resistance element coupled between the fifth interconnect and the ground node;
a seventh resistance element coupled between the sixth interconnect and the ground node; and
an eighth resistance element coupled between the fifth interconnect and the anodes of the M fourth diodes, and
wherein the second BGR circuit is configured to output a voltage of the sixth interconnect as the third voltage.
12. The device according to claim 11 , wherein, when a temperature characteristic value of a built-in potential of the fourth diode is −2[mV/° C.],
a resistance value of the fourth resistance element is R 1 , and
a resistance value of the sixth resistance element is R 3 ,
a following relationship is established:
(R1/R3)·( k/q )·ln M< 2[mV]
wherein k is a Boltzmann constant and q is a charge amount of electrons.
13. The device according to claim 11 , wherein the first circuit is configured to:
compare the fourth voltage with the fifth voltage,
apply the second voltage as the first voltage when the fourth voltage is higher than the fifth voltage, and
apply the third voltage as the first voltage when the fourth voltage is lower than the fifth voltage.
14. The device according to claim 11 , wherein the first voltage generator further includes:
a seventh transistor of the first conductivity type in which the power-supply voltage is applied to a source, the fourth voltage is applied to a gate, and a drain is coupled to a seventh interconnect; and
a ninth resistance element coupled between the seventh interconnect and the ground node,
wherein the second voltage generator further includes:
an eighth transistor of the first conductivity type in which the power-supply voltage is applied to a source, the fifth voltage is applied to a gate, and a drain is coupled to an eighth interconnect; and
a tenth resistance element coupled between the eighth interconnect and the ground node, and
wherein the first circuit is configured to:
compare a voltage of the seventh interconnect with a voltage of the eighth interconnect,
apply the second voltage as the first voltage when the voltage of the seventh interconnect is lower than the voltage of the eighth interconnect, and
apply the third voltage as the first voltage when the voltage of the seventh interconnect is higher than the voltage of the eighth interconnect.
15. A semiconductor storage device comprising:
a memory cell including a variable resistance element;
a bit line coupled to the memory cell; and
a first circuit configured to apply a first current to the bit line in a write operation for the memory cell, a temperature coefficient of the first current being negative,
wherein the first current flows through the memory cell when a state of the variable resistance element is changed from a low resistance state to a high resistance state.
16. The device according to claim 15 , wherein the variable resistance element is an interfacial phase change memory element (iPCM element) or a super lattice phase-change element.
17. The device according to claim 15 , wherein the first circuit includes:
a first BGR circuit configured to generate a second current, a temperature coefficient of the second current being 0; and
a second BGR circuit configured to generate a third current, a temperature coefficient of the third current being negative, and
wherein the first circuit is configured to apply a sum of the second current and the third current as the first current.
18. A semiconductor storage device comprising:
a memory cell including a variable resistance element;
a bit line coupled to the memory cell;
a sense amplifier coupled to the bit line; and
a first circuit configured to apply a first reference voltage to the sense amplifier in a reading operation for the memory cell, a temperature coefficient of the first reference voltage being negative,
wherein, in the reading operation for the memory cell, the temperature coefficient of the first reference voltage is lower than a temperature coefficient of a first voltage of the bit line obtained when the variable resistance element is in a high resistance state, and is higher than a temperature coefficient of a second voltage of the bit line obtained when the variable resistance element is in a low resistance state.
19. The device according to claim 18 , wherein in the reading operation for the memory cell, the first reference voltage is approximately equal to a mean value of the first voltage and the second voltage.
20. The device according to claim 19 , wherein the variable resistance element is an interfacial phase change memory element (iPCM element) or a super lattice phase-change element.
21. A semiconductor storage device comprising:
a memory cell including a variable resistance element;
a bit line coupled to the memory cell; and
a first circuit configured to apply a first voltage to the bit line in a write operation for the memory cell,
wherein:
the first voltage has a first voltage value when a temperature of the semiconductor storage device is a second temperature value, the second temperature value being lower than a first temperature value,
the first voltage has a second voltage value when the temperature of the semiconductor storage device is a third temperature value, the third temperature value being higher than the second temperature value by a given value, and the third temperature value being lower than the first temperature value,
the first voltage has a third voltage value when the temperature of the semiconductor storage device is a fourth temperature value, the fourth temperature value being higher than the first temperature value,
the first voltage has a fourth voltage value when the temperature of the semiconductor storage device is a fifth temperature value, the fifth temperature value being higher than the fourth temperature value by the given value, and
a difference between the first voltage value and the second voltage value is smaller than a difference between the third voltage value and the fourth voltage value.
22. The device according to claim 21 , wherein the difference between the first voltage value and the second voltage value is 0.
23. The device according to claim 21 , wherein:
the first circuit includes:
a first voltage generator configured to generate a second voltage; and
a second voltage generator configured to generate a third voltage, a temperature coefficient of the third voltage being lower than a temperature coefficient of the second voltage,
the first circuit is configured apply a lower one of the second voltage and the third voltage as the first voltage in the write operation, and
the second voltage is equal to the third voltage when the temperature of the semiconductor storage device is at the first temperature value.
24. The device according to claim 23 , wherein:
the first voltage generator includes a first bandgap reference (BGR) circuit configured to generate the second voltage, and
the second voltage generator includes a second BGR circuit configured to generate the third voltage.
25. The device according to claim 24 , wherein the first BGR circuit includes:
a first transistor of a first conductivity type in which a power-supply voltage is applied to a source, and a drain is coupled to a first interconnect;
a second transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to a second interconnect;
a third transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to a third interconnect;
a first operational amplifier configured to compare a voltage of the first interconnect with a voltage of the second interconnect, and apply a fourth voltage corresponding to a comparison result by the first operational amplifier to gates of the first to third transistors;
a first diode in which an anode is coupled to the first interconnect, and a cathode is coupled to a ground node;
N (N is an integer greater than or equal to 2) second diodes in which cathodes are coupled to the ground node and anodes are coupled to each other;
a first resistance element coupled between the first interconnect and the ground node;
a second resistance element coupled between the second interconnect and the ground node;
a third resistance element coupled between the third interconnect and the ground node; and
a fourth resistance element coupled between the second interconnect and the anodes of the N second diodes, and
wherein the first BGR circuit is configured to output a voltage of the third interconnect as the second voltage.
26. The device according to claim 25 , wherein, when a temperature characteristic value of a built-in potential of the second diode is −2[mV/° C.],
a resistance value of the first resistance element is R 1 , and
a resistance value of the fourth resistance element is R 3 ,
a following relationship is established:
( R 1/ R 3)·( k/q )·ln N= 2[mV],
wherein k is a Boltzmann constant and q is a charge amount of electrons.
27. The device according to claim 25 , wherein the second BGR circuit includes:
a fourth transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to fourth interconnect;
a fifth transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to fifth interconnect;
a sixth transistor of the first conductivity type in which the power-supply voltage is applied to a source, and a drain is coupled to sixth interconnect;
a second operational amplifier configured to compare a voltage of the fourth interconnect with a voltage of the fifth interconnect, and apply a fifth voltage corresponding to a comparison result by the second operational amplifier to gates of the fourth to sixth transistors;
a third diode in which an anode is coupled to the fourth interconnect and a cathode is coupled to the ground node;
M (M is an integer greater than or equal to 2) fourth diodes in which cathodes are coupled to the ground node and anodes are coupled to each other;
a fifth resistance element coupled between the fourth interconnect and the ground node;
a sixth resistance element coupled between the fifth interconnect and the ground node;
a seventh resistance element coupled between the sixth interconnect and the ground node; and
an eighth resistance element coupled between the fifth interconnect and the anodes of the M fourth diodes, and
wherein the second BGR circuit is configured to output a voltage of the sixth interconnect as the third voltage.
28. The device according to claim 27 wherein, when a temperature characteristic value of a built-in potential of the fourth diode is −2[mV/° C.],
a resistance value of the fourth resistance element is R 1 , and
a resistance value of the sixth resistance element is R 3 ,
a following relationship is established:
( R 1/ R 3)·( k/q )·ln M< 2[mV]
wherein k is a Boltzmann constant and q is a charge amount of electrons.
29. The device according to claim 27 , wherein the first circuit is configured to compare the fourth voltage with the fifth voltage, apply the second voltage as the first voltage when the fourth voltage is higher than the fifth voltage, and apply the third voltage as the first voltage when the fourth voltage is lower than the fifth voltage.
30. The device according to claim 27 , wherein the first voltage generator further includes:
a seventh transistor of the first conductivity type in which the power-supply voltage is applied to a source, the fourth voltage is applied to a gate, and a drain is coupled to a seventh interconnect; and
a ninth resistance element coupled between the seventh interconnect and the ground node,
wherein the second voltage generator further includes:
an eighth transistor of the first conductivity type in which the power-supply voltage is applied to a source, the fifth voltage is applied to a gate, and a drain is coupled to an eighth interconnect; and
a tenth resistance element coupled between the eighth interconnect and the ground node, and
wherein the first circuit is configured to:
compare a voltage of the seventh interconnect with a voltage of the eighth interconnect,
apply the second voltage as the first voltage when the voltage of the seventh interconnect is lower than the voltage of the eighth interconnect, and
apply the third voltage as the first voltage when the voltage of the seventh interconnect is higher than the voltage of the eighth interconnect.
31. The device according to claim 23 , wherein:
the first circuit further includes a voltage selection circuit configured to select the lower one of the second voltage and the third voltage,
the voltage selection circuit includes:
a first transistor of a first conductivity type in which a power-supply voltage is applied to a source;
a second transistor of the first conductivity type in which a source is coupled to a drain of the first transistor and a drain is coupled to a first interconnect;
a first operational amplifier configured to compare the second voltage with a voltage of the first interconnect, and apply a voltage corresponding to a comparison result by the first operational amplifier to a gate of the first transistor;
a second operational amplifier configured to compare the third voltage with the voltage of the first interconnect, and apply a voltage corresponding to a comparison result by the second operational amplifier to a gate of the second transistor; and
a first resistance element coupled between the first interconnect and a ground node, and
the first circuit is configured to output the voltage of the first interconnect as the first voltage.
32. The device according to claim 23 , wherein:
the first circuit includes a voltage selection circuit configured to select the lower one of the second voltage and the third voltage,
the voltage selection circuit includes:
a first transistor of a first conductivity type in which a drain is coupled to a first interconnect and a source is applied with a ground voltage;
a second transistor of the first conductivity type in which a drain is coupled to the first interconnect and a source is applied with the ground voltage;
a first operational amplifier configured to compare the second voltage with a voltage of the first interconnect and apply a voltage corresponding to a comparison result by the first operational amplifier to a gate of the first transistor;
a second operational amplifier configured to compare the third voltage with the voltage of the first interconnect and apply a voltage corresponding to a comparison result by the second operational amplifier to a gate of the second transistor;
a first resistance element coupled between the first interconnect and a power supply node, and
the first circuit is configured to output the voltage of the first interconnect as the first voltage.
33. The device according to claim 23 , wherein the second voltage generator includes:
a first BGR circuit configured to generate a first current; and
a second BGR circuit configured to generate a second current, a temperature coefficient of the second current being lower than a temperature coefficient of the first current, and
wherein the second voltage generator is configured to generate the third voltage based on a sum of the first current and the second current.
34. The device according to claim 21 , wherein the first voltage is applied to the memory cell when a state of the variable resistance element is changed from a high resistance state to a low resistance state.
35. The device according to claim 21 , wherein the variable resistance element is an interfacial phase change memory element (iPCM element) or a super lattice phase-change element.