Test circuit for stress leakage measurements
In accordance with an embodiment, a circuit includes: a gate drive circuit; an output transistor, and a gate coupled to the gate drive circuit; a normally-on transistor including a load path coupled to the gate drive circuit and to the gate of the output transistor; and a pull-up device, where the output transistor is configured to provide a test leakage current in a test mode when a measurement voltage is applied to a current test node coupled to the gate of the output transistor and a turn-off voltage is applied to the gate of the normally-on transistor; and the gate drive circuit is configured to provide a gate drive voltage to the gate of the output transistor in a nominal operation mode when a voltage of the gate of the normally-on transistor is pulled-up to a voltage of the pull-up node via the pull-up device.
1. A circuit comprising:
a gate drive circuit;
an output transistor having a first load path coupled between a supply node and an output node, and a gate coupled to the gate drive circuit;
a normally-on transistor comprising a second load path coupled to the gate drive circuit and to the gate of the output transistor; and
a pull-up device coupled between a gate of the normally-on transistor and a pull-up node, wherein
the output transistor is configured to provide a test leakage current in a test mode when a measurement voltage is applied to a current test node coupled to the gate of the output transistor and a turn-off voltage is applied to the gate of the normally-on transistor; and
the gate drive circuit is configured to provide a gate drive voltage to the gate of the output transistor in a nominal operation mode when a voltage of the gate of the normally-on transistor is pulled-up to a voltage of the pull-up node via the pull-up device.
2. The circuit of claim 1 , wherein
the pull-up device comprises a resistor, and
the normally-on transistor comprises a depletion MOS transistor.
3. The circuit of claim 2 , wherein the depletion MOS transistor is an NMOS transistor.
4. The circuit of claim 1 , further comprising:
a first voltage generator coupled to the a gate of the normally-on transistor, the first voltage generator configured to provide the turn-off voltage; and
a second circuit coupled to the current test node, the second circuit comprising
a second voltage generator configured to provide the measurement voltage, and
a current measurement circuit configured to measure the test leakage current.
5. The circuit of claim 4 , wherein the first voltage generator provides the turn-off voltage while the second voltage generator provides the measurement voltage and the current measurement circuit measures the test leakage current.
6. The circuit of claim 5 , wherein the circuit is categorized as having a defect when the test leakage current is bigger than a reference current.
7. The circuit of claim 4 , wherein the first voltage generator and the second circuit are circuits of an automatic test equipment (ATE).
8. The circuit of claim 4 , wherein the first voltage generator and the second circuit are circuits of the same integrated circuit.
9. The circuit of claim 4 , wherein
the test leakage current is negative,
the turn-off voltage is negative, and
the measurement voltage is zero.
10. The circuit of claim 1 , wherein
the output transistor comprises an NMOS transistor having a second source coupled to ground and a second drain; and
the gate drive circuit comprises
a third transistor coupled to an output of the gate drive circuit, and
a fourth transistor coupled to the output of the gate drive circuit.
11. The circuit of claim 1 , wherein
the output transistor is a PMOS transistor; and
the gate drive circuit comprises
a third transistor coupled to an output of the gate drive circuit, and
a fourth transistor coupled to the output of the gate drive circuit.
12. The circuit of claim 11 , wherein
the second load path is coupled between the gate drive circuit and the supply node of the output transistor; and
the pull-up node comprises the supply node.
13. The circuit of claim 11 , further comprising a bias circuit coupled to the gate of the normally-on transistor, wherein the second load path is coupled between the gate drive circuit and the gate of the output transistor.
14. The circuit of claim 1 , wherein
the output transistor is a PMOS transistor; and
the gate drive circuit comprises a third transistor coupled to an output of the gate drive circuit, the third transistor configured to mirror a polarization current into the first load path.
15. The circuit of claim 14 , wherein
the second load path is coupled between the gate drive circuit and a source of the output transistor; and
the pull-up node comprises the source of the output transistor.
16. The circuit of claim 14 , wherein the second load path is coupled between the gate drive circuit and the gate of the output transistor; and
the pull-up node comprises the supply node.
17. The circuit of claim 1 , wherein the gate drive circuit is configured to provide a gate drive voltage to the gate of the output transistor in a power-down state when a voltage of the gate of the normally-on transistor is pulled-up to the pull-up node via the pull-up device.
18. The circuit of claim 1 , wherein the pull-up device comprises a transistor.
19. A method of operating a device comprising a first transistor, the method comprising:
performing a leakage stress testing operation comprising
preventing a current from flowing between a gate of the first transistor and a third circuit by turning off a normally-on transistor coupled to the gate of the first transistor and to the third circuit,
applying a first stress voltage to the gate of the first transistor, and
measuring a first current flowing from the gate of the first transistor; and
performing, by the device, a normal operation comprising turning on the normally-on transistor.
20. The method of claim 19 , further comprising performing a power down operation comprising turning on the normally-on transistor.
21. The method of claim 19 , wherein the leakage stress testing operation further comprises applying a second stress voltage to a source of the first transistor.
22. The method of claim 21 , wherein the source of the first transistor is coupled to a drain of the first transistor.
23. The method of claim 21 , wherein
the third circuit controls the gate of the first transistor;
applying the first stress voltage comprises applying 8 V; and
applying the second stress voltage comprises applying 2 V.
24. The method of claim 19 , wherein the turning on the normally-on transistor comprises pulling up a gate of the normally-on transistor to a pull-up node.
25. The method of claim 24 , wherein the pull-up node is coupled to a source of the normally-on transistor.
26. The method of claim 19 , wherein the turning on the normally-on transistor comprises pulling up a gate of the normally-on transistor by a bias circuit.
27. The method of claim 19 , wherein the turning on the normally-on transistor comprises pulling up a gate of the normally-on transistor to a source of the first transistor.
28. The method of claim 19 , further comprising categorizing the device as good if the first current is lower than a predetermined current, and categorizing the device as bad if the first current is higher than the predetermined current.
29. A circuit comprising:
an integrated circuit comprising
a first circuit,
an output transistor having a first load path coupled between a supply node and an output node, and a gate coupled to the first circuit,
a first test node coupled to the gate of the output transistor,
a depletion NMOS transistor comprising a second load path coupled between the first circuit and the gate of the output transistor,
a second test node coupled to a gate of the depletion NMOS transistor, and
a pull-up element coupled between the gate of the depletion NMOS transistor and a pull-up node.
30. The circuit of claim 29 , further comprising
a first voltage generator coupled to the second test node and configured to provide a first stress voltage;
a second voltage generator coupled to the first test node and configured to provide a measurement voltage; and
a current measurement circuit coupled to the second voltage generator and configured to measure leakage current.
31. The circuit of claim 29 , wherein the pull-up element comprises a transistor.