Storage system, information processing system and method for controlling nonvolatile memory

1. A memory system comprising:

a nonvolatile memory including a plurality of blocks, each of the blocks being a unit for erasing data from the nonvolatile memory; and

a controller electrically connected to the nonvolatile memory,

wherein the controller is configured to:

classify the plurality of blocks into a first plurality of first blocks and a second plurality of second blocks, the first blocks being accessed block by block independently of each other and managed by the controller as blocks dedicated to be accessed block by block, the second blocks being organized as a plurality of block groups, each of the block groups including a third plurality of third blocks being accessed in parallel and managed by the controller as blocks dedicated to be accessed in parallel, the first blocks and the second blocks having no overlapping block;

when a host requests an allocation of one block, allocate one first block in the first blocks for the host, and notify the host of a first physical address designating the allocated one first block, wherein the first physical address indicates a physical address of the nonvolatile memory in a unit of a block;

when receiving, from the host, a first read or write command including the first physical address, perform a first read or write operation on the allocated one first block designated by the first physical address;

when the host requests an allocation of one block group, allocate one block group in the block groups for the host, and notify the host of a second physical address designating the allocated one block group, wherein the second physical address indicates another physical address of the nonvolatile memory in another unit of a block group; and

when receiving, from the host, a second read or write command including the second physical address, perform a second read or write operation on blocks included in the allocated one block group designated by the second physical address, wherein the blocks are accessed in parallel.

2. The memory system of claim 1 , wherein a combination of physical addresses of blocks belonging to each of the block groups is determined from a physical address designating said each of the block groups, based on a mathematical rule.

3. The memory system of claim 2 , wherein when the combination of physical addresses of blocks determined based on the mathematical rule includes a physical address designating a bad block, the controller selects another block which is accessible in parallel with all blocks of the first block group excluding the bad block, and replaces the bad block with the selected block.

4. The memory system of claim 1 , wherein

the controller is further configured to:

manage block erase counts of the respective first blocks;

manage block group erase counts of the respective block groups;

notify the host of a block erase count of one first block in the first blocks when the host requests an acquisition of the block erase count of the one first block; and

notify the host of a block group erase count of one block group in the block groups when the host requests another acquisition of the block group erase count of the one block group.

5. The memory system of claim 1 , wherein

the controller is further configured to:

manage valid data blocks included in the first blocks and holding valid data, and invalid data blocks included in the first blocks and holding no valid data;

manage valid data block groups included in the block groups and holding valid data, and invalid data block groups included in the block groups and holding no valid data;

allocate, for the host, one block included in the invalid data blocks, erase the allocated one block, and notify the host of a physical address designating the allocated and erased one block, when the host requests both the allocation of the one block and the erasure of the one block; and

allocate, for the host, one block group included in the invalid data block groups, erase the allocated one block group, and notify the host of a physical address designating the allocated and erased one block group, when the host requests both the allocation of the one block group and the erasure of the one block group.

6. The memory system of claim 5 , wherein

the controller is further configured to:

manage block erase counts of the respective first blocks, and block group erase counts of the respective block groups;

select, from the invalid data blocks, a block having a minimum block erase count as the one block to be allocated for the host, when the host requests both the allocation of the one block and the erasure of the one block; and

select, from the invalid data block group, a block group having a minimum block group erase count as the one block group to be allocated for the host, when the host requests both the allocation of the one block group and the erasure of the one block group.

7. An information processing system comprising a memory system and a host, wherein

the memory system comprises:

a nonvolatile memory including a plurality of blocks, each of the blocks being a unit for erasing data from the nonvolatile memory; and

a controller electrically connected to the nonvolatile memory, and configured to classify the plurality of blocks into a first plurality of first blocks and a second plurality of second blocks, the first blocks being accessed block by block independently of each other and managed by the controller as blocks dedicated to be accessed block by block, the second blocks being organized as a plurality of block groups, each of the block groups including a third plurality of third blocks being accessed in parallel and managed by the controller as blocks dedicated to be accessed in parallel, the first blocks and the second blocks having no overlapping block;

the host comprises:

a memory; and

a processor configured to execute a program stored in the memory,

wherein the processor is configured to:

transmit, to the memory system, a first command to instruct allocation of one block; and

transmit, to the memory system, a second command to instruct allocation of one block group,

wherein the controller is configured to:

when receiving the first command, allocate one first block in the first blocks for the host, and notify the host of a first physical address designating the allocated one first block, wherein the first physical address indicates a physical address of the nonvolatile memory in a unit of a block;

when receiving the second command, allocate one block group in the block groups for the host, and notify the host of a second physical address designating the allocated one block group, wherein the second physical address indicates another physical address of the nonvolatile memory in another unit of a block group;

wherein the processor is configured to:

transmit, to the memory system, a first read or write command including the first physical address; and

transmit, to the memory system, a second read or write command including the second physical address, and

wherein the controller is configured to:

perform a first read or write operation on the allocated one first block designated by the first physical address; and

perform a second read or write operation on blocks included in the allocated one block group designated by the second physical address, wherein the blocks are accessed in parallel.

8. A control method of controlling a nonvolatile memory in a memory system, the nonvolatile memory including a plurality of blocks, each of the blocks being a unit for erasing data from the nonvolatile memory, the memory system including the nonvolatile memory and a controller, the control method comprising:

classifying the plurality of blocks into a first plurality of first blocks and a second plurality of second blocks, the first blocks being accessed block by block independently of each other and managed by the controller as blocks dedicated to be accessed block by block, the second blocks being organized as a plurality of block groups, each of the block groups including a third plurality of third blocks being accessed in parallel and managed by the controller as blocks dedicated to be accessed in parallel, the first block and the second blocks having no overlapping block;

when a host requests an allocation of one block, allocating one first block in the first blocks for the host, and notifying the host of a first physical address designating the allocated one first block, wherein the first physical address indicates a physical address of the nonvolatile memory in a unit of a block;

when receiving, from the host, a first read or write command including the first physical address, performing a first read or write operation on the allocated one first block designated by the first physical address;

when the host requests an allocation of one block group, allocating one block group in the block groups for the host, and notifying the host of a second physical address designating the allocated one block group, wherein the second physical address indicates another physical address of the nonvolatile memory in another unit of a block group; and

when receiving, from the host, a second read or write command including the second physical address, performing a second read or write operation on blocks included in the allocated one block group designated by the second physical address, wherein the blocks are accessed in parallel.

9. The control method of claim 8 , further comprising:

managing valid data blocks included in the first blocks and holding valid data, and invalid data blocks included in the first blocks and holding no valid data;

managing valid data block groups included in the block groups and holding valid data, and invalid data block groups included in the block groups and holding no valid data;

allocating, for the host, one block included in the invalid data blocks, erasing the allocated one block, and notifying the host of a physical address designating the allocated and erased one block, when the host requests both the allocation of the one block and the erasure of the one block; and

allocating, for the host, one block group included in the invalid data block groups, erasing the allocated one block group, and notifying the host of a physical address designating the allocated and erased one block group, when the host requests both the allocation of the one block group and the erasure of the one block group.

10. The control method of claim 9 , further comprising:

managing block erase counts of the respective first blocks, and block group erase counts of the respective block groups;

selecting, from the invalid data blocks, a block having a minimum block erase count as the one block to be allocated for the host, when the host requests both the allocation of the one block and the erasure of the one block; and

selecting, from the invalid data block groups, a block group having a minimum block group erase count as the one block group to be allocated for the host, when the host requests both the allocation of the one block group and the erasure of the one block group.

11. A memory system comprising:

a nonvolatile memory including a plurality of blocks, each of the blocks being a unit for erasing data from the nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to:

classify the plurality of blocks into a first plurality of first blocks and a second plurality of second blocks, the first blocks being accessed block by block independently of each other and managed by the controller as blocks dedicated to be accessed block by block, the second blocks being organized as a plurality of block groups, each of the block groups including a third plurality of third blocks being accessed in parallel and managed by the controller as blocks dedicated to be accessed in parallel, the first blocks and the second blocks having no overlapping block,

in response to receiving a first command from a host, the first command designating a first physical address that indicates a physical address of the nonvolatile memory in a unit of a block,

access a block designated by the first physical address, and

in response to receiving a second command from the host, the second command designating a second physical address that indicates another physical address of the nonvolatile memory in a unit of a block group,

access, in parallel, at least two blocks of a block group designated by the second physical address.