Electronic device with periphery contact pads surrounding central contact pads

1. A semiconductor device comprising:

an integrated circuit;

an encapsulating material overlying an upper surface of the integrated circuit;

a plurality external contacts disposed at an outer surface of the encapsulating material;

wherein each of the external contacts is electrically connected to the integrated circuit;

wherein ones of the external contacts are electrically connected to the integrated circuit via wire bonds; and

wherein other ones of the external contacts are electrically connected to the integrated circuit via conductive vias without any wire bonds.

2. The device of claim 1 , further comprising a heat sink thermally coupled to a lower surface of the integrated circuit, the lower surface opposite the upper surface.

3. The device of claim 2 , further comprising a thermally conductive adhesive material disposed between the lower surface of the integrated circuit and the heat sink.

4. The device of claim 1 , wherein the integrated circuit has an upper surface that includes a central region and a peripheral region that surrounds the central region, wherein a plurality of central bond pads are disposed in the central region and a plurality of periphery bond pads are disposed in the peripheral region, wherein the ones of the external contacts comprise periphery contacts that are electrically connected to respective ones of the periphery bond pads, and wherein the other ones of the external contacts comprise central contacts that are electrically connected to respective ones of the central bond pads.

5. The device of claim 4 , wherein each of the periphery contacts includes a sidewall exposed on a corresponding side of the encapsulating material.

6. The device of claim 4 , wherein each of the periphery contacts extends from the outer surface of the encapsulating material to a lower surface of the encapsulating material.

7. The device of claim 6 , further comprising a second integrated circuit that physically attached at the lower surface of the encapsulating material and is electrically coupled the integrated circuit through the periphery contacts.

8. The device of claim 1 , wherein each of the other ones of the external contacts comprises a single conductive via that extends from a respective central bond pad to the outer surface of the encapsulating material.

9. The device of claim 1 , wherein the other ones of the external contacts comprise an interposer disposed between the upper surface of the integrated circuit and the outer surface of the encapsulating material.

10. The device of claim 9 , wherein the interposer comprises a semiconductor substrate and a plurality of conductive vias extending through the semiconductor substrate.

11. The device of claim 9 , wherein the interposer is coupled to the integrated circuit using electrically conductive paste or reflow solder.

12. The device of claim 9 , further comprising a plurality of solder bodies disposed between the integrated circuit and the interposer.

13. The device of claim 1 , wherein the external contacts are arranged in a plurality of rows, each row including a plurality of the external contacts.

14. The device of claim 1 , wherein the ones of the external contacts each comprise a conductive material that extends through the encapsulating material, the conductive material electrically connected to the integrated circuit through a respective wire bond.

15. The device of claim 1 , wherein the other ones of the external contacts comprise an interposer.

16. A semiconductor device comprising:

an integrated circuit having an upper surface that includes a central region and a peripheral region that surrounds the central region, a plurality of central bond pads being disposed in the central region and a plurality of periphery bond pads being disposed in the peripheral region;

a plurality of periphery leads surrounding the integrated circuit and spaced therefrom;

a plurality of bond wires electrically connecting each of the periphery bond pads to a respective one of the periphery leads;

a plurality of central leads, each central lead being electrically connected to a respective one of the central bond pads; and

an encapsulating material formed over the upper surface of the integrated circuit and between the periphery leads and the integrated circuit, the periphery leads and the central leads extending to an outer surface of the encapsulating material so as to be accessible for electrical connection to the integrated circuit.

17. The device of claim 16 , further comprising a heat sink thermally coupled to a lower surface of the integrated circuit, the lower surface opposite the upper surface.

18. The device of claim 17 , further comprising a thermally conductive adhesive material disposed between the lower surface of the integrated circuit and the heat sink.

19. The device of claim 17 , wherein the encapsulating material is in contact with the heat sink.

20. The device of claim 16 , wherein each of the periphery leads includes a sidewall exposed on a corresponding side of the encapsulating material.

21. The device of claim 16 , wherein each of the periphery leads extends from the outer surface of the encapsulating material to a lower surface of the encapsulating material.

22. The device of claim 21 , further comprising a second integrated circuit that physically attached at the lower surface of the encapsulating material and is electrically coupled the integrated circuit through the periphery leads.

23. The device of claim 16 , wherein each of the central leads comprises a single conductive via that extends from the respective central bond pad to the outer surface of the encapsulating material.

24. The device of claim 16 , wherein the central leads comprise an interposer disposed between the upper surface of the integrated circuit and the outer surface of the encapsulating material.

25. The device of claim 24 , wherein the interposer comprises a semiconductor substrate and a plurality of conductive vias extending through the semiconductor substrate.

26. The device of claim 24 , wherein the interposer is coupled to the central bond pads using electrically conductive paste or reflow solder.

27. The device of claim 24 , further comprising a plurality of solder bodies disposed between the plurality of central bond pads and the interposer.

28. A quad-flat no-leads (QFN) packaged device comprising:

an integrated circuit having an upper surface that includes a peripheral region that surrounds a central region, a plurality of central bond pads being disposed in the central region and a plurality of periphery bond pads being disposed in the peripheral region;

a heat sink thermally coupled to a lower surface of the integrated circuit, the lower surface being opposite the upper surface;

an encapsulating material, wherein the integrated circuit is encapsulated within the encapsulating material, wherein the heat sink is exposed at a lower surface of the encapsulating material;

a plurality of periphery leads surrounding the integrated circuit and spaced therefrom by the encapsulating material, each periphery lead being L-shaped with a lower portion extending toward the integrated circuit, wherein an upper portion of each periphery lead is exposed at an upper surface of the encapsulating material and a lower portion of each periphery lead is exposed at the lower surface of the encapsulating material;

a plurality of bond wires electrically connecting each of the periphery bond pads to the lower portion a respective one of the periphery leads; and

a plurality of central leads, each central lead being electrically connected to a respective one of the central bond pads and extending to the upper surface of the encapsulating material, wherein the upper portions of the periphery leads and the central leads form a plurality of rows of external contacts.

29. The device of claim 28 , wherein each of the periphery leads includes a sidewall exposed on a corresponding side of the encapsulating material.

30. The device of claim 28 , wherein each of the central leads comprises a single conductive via that extends from the respective central bond pad to the upper surface of the encapsulating material.

31. The device of claim 28 , wherein the central leads comprise an interposer disposed between the upper surface of the integrated circuit and the upper surface of the encapsulating material.

32. The device of claim 28 wherein, the lower portion of each periphery lead is spaced from the heat sink.

33. A quad-flat no-leads (QFN) packaged device comprising:

an integrated circuit comprising

a first major surface that includes an outer region that surrounds an interior region,

interior bond pads disposed in the interior region,

outer bond pads disposed in the outer region, and

a second major surface opposite to the first major surface;

an encapsulating material surrounding the integrated circuit and covering the first major surface, the encapsulating material comprising a third major surface facing away from the integrated circuit;

interior connectors disposed over the interior region of the first major surface, each interior connector being electrically connected to a respective one of the interior bond pads and extending to the third major surface of the encapsulating material; and

outer leads surrounding the integrated circuit, each outer lead being electrically connected to a respective one of the outer bond pads and extending to the third major surface of the encapsulating material, wherein upper portions of the outer leads and the interior connectors are part of an array of external contacts of the QFN package device.

34. The device of claim 33 , wherein the interior connectors and the outer leads are disposed in the encapsulating material.

35. The device of claim 33 , wherein the interior connectors comprise an interposer disposed between the first major surface of the integrated circuit and the third major surface of the encapsulating material.

36. The device of claim 35 , further comprising a semiconductor substrate disposed over the first major surface of the integrated circuit, wherein the interposer is disposed in the semiconductor substrate and a plurality of conductive vias extend through the semiconductor substrate.

37. The device of claim 35 , wherein the interposer is coupled to the interior bond pads using electrically conductive paste or reflow solder.

38. The device of claim 35 , further comprising a plurality of solder bodies disposed between the interior bond pads and the interposer.

39. The device of claim 33 , further comprising a heat sink thermally coupled to the second major surface of the integrated circuit.