IP Library Granted Patent US 10,201,084
Granted Patent B2
US 10,201,084 · App. 15/251,699 · Granted Feb 5, 2019

Printed circuit board via design

Inventors: V. Mallikarjun Goud (Secunderabad, IN); Bhyrav M. Mutnury (Round Rock, TX)
Assignee: Dell Products, LP
H05K1/115H01R13/6461H01R13/6467H05K1/0245H05K3/0005H01R12/732H05K1/114H05K1/142H05K2201/0949H05K2201/09227H05K2201/10189
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Quick Facts
Patent No.
US 10,201,084
App. No.
15/251,699
Granted
Feb 5, 2019
Kind
B2
Abstract

A printed circuit board includes vias of first and second differential pairs, and vias of third and fourth differential pairs. The vias of the first and second differential pairs are arranged in a first via pattern based on a first crosstalk signature of a first connector to be coupled to the vias of the first and second differential pairs. The vias of the third and fourth differential pairs are arranged in a second via pattern based on a second crosstalk signature of a second connector to be coupled to the vias of the third and fourth differential pairs.

Claims (27)

1. A printed circuit board comprising:

vias of first and second differential pairs arranged in a first via pattern, wherein the vias of the first and second differential pairs are arranged in the first via pattern based on a first crosstalk signature of a first connector to be coupled to the vias of the first and second differential pairs; and

vias of third and fourth differential pairs arranged in a second via pattern, wherein the vias of the third and fourth differential pairs are arranged in the second via pattern based on a second crosstalk signature of a second connector to be coupled to the vias of the third and fourth differential pairs.

2. The printed circuit board of claim 1 , wherein the vias of the first and second differential pairs are arranged in the first via pattern further based on a third crosstalk signature of the vias of the first and second differential pairs in the first via pattern.

3. The printed circuit board of claim 1 , wherein the vias of the third and fourth differential pairs are arranged in the second via pattern further based on a third crosstalk signature of the vias of the third and fourth differential pairs in the second via pattern.

4. The printed circuit board of claim 1 , wherein the first via pattern and the second via pattern are the same via pattern.

5. The printed circuit board of claim 1 , wherein the vias of the first and second differential pairs arranged in the first via pattern negates crosstalk in the first connector.

6. The printed circuit board of claim 1 , wherein the vias of the third and fourth differential pairs arranged in the second via pattern negates crosstalk in the second connector.

7. The printed circuit board of claim 6 , wherein the first via pattern is selected from a group consisting of a straight pattern, a parallel pattern, a half via staggered parallel pattern, a one via staggered parallel pattern, a two via staggered parallel pattern, and a two and a half via staggered parallel pattern.

8. A printed circuit board comprising:

first vias of a first differential pair; and

second vias of a second differential pair arranged in a first via pattern with the first vias, wherein the first and second vias are arranged in the first via pattern based on a first crosstalk signature of a first connector to be coupled to the vias of the first and second differential pairs.

9. The printed circuit board of claim 8 , wherein the first and second vias are arranged in the first via pattern further based on a third crosstalk signature of the first and second vias in the first via pattern.

10. The printed circuit board of claim 8 , wherein the first and second vias arranged in the first via pattern negates crosstalk in the first connector.

11. The printed circuit board of claim 8 , wherein the first via pattern is selected from a group consisting of a straight pattern, a parallel pattern, a half via staggered parallel pattern, a one via staggered parallel pattern, a two via staggered parallel pattern, and a two and a half via staggered parallel pattern.

12. The printed circuit board of claim 8 , further comprising:

vias of third and fourth differential pairs arranged in a second via pattern, wherein the vias of the third and fourth differential pairs are arranged in the second via pattern based on a second crosstalk signature of a second connector to be coupled to the vias of the third and fourth differential pairs and based on a third crosstalk signature of the vias of the third and fourth differential pairs in the second via pattern, wherein the vias of the third and fourth differential pairs arranged in the second via pattern negates crosstalk in the second connector.

13. The printed circuit board of claim 12 , wherein the first via pattern and the second via pattern are the same via pattern.

14. The printed circuit board of claim 8 , wherein the first and second vias are placed at first location of the printed circuit board based on a second location that the first connector is coupled to the printed circuit board.

15. The printed circuit board of claim 14 , wherein the first via pattern and the second via pattern are the same via pattern.

16. The printed circuit board of claim 14 , wherein the vias of the first and second differential pairs arranged in the first via pattern negates crosstalk in the first connector.

17. The printed circuit board of claim 14 , wherein the vias of the third and fourth differential pairs arranged in the second via pattern negates crosstalk in the second connector.

18. The printed circuit board of claim 14 , wherein the first via pattern is selected from a group consisting of a straight pattern, a parallel pattern, a half via staggered parallel pattern, a one via staggered parallel pattern, a two via staggered parallel pattern, and a two and a half via staggered parallel pattern.

19. The printed circuit board of claim 14 , wherein the first and second vias are placed at first location of the printed circuit board based on a second location that the first connector is coupled to the printed circuit board.

20. A printed circuit board comprising:

vias of first and second differential pairs arranged in a first via pattern, wherein the vias of the first and second differential pairs are arranged in the first via pattern based on a first crosstalk signature of a first connector to be coupled to the vias of the first and second differential pairs and based on a second crosstalk signature of the vias of the first and second differential pairs in the first via pattern; and

vias of third and fourth differential pairs arranged in a second via pattern, wherein the vias of the third and fourth differential pairs are arranged in the second via pattern based on a third crosstalk signature of a second connector to be coupled to the vias of the third and fourth differential pairs and based on a fourth crosstalk signature of the vias of the third and fourth differential pairs in the second via pattern.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (050724/0466) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 060753/0486 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040679/0386) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0666 →
RELEASE OF SECURITY INTEREST AT REEL 040633 FRAME 0799 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL INTERNATIONAL, L.L.C.; DELL PRODUCTS L.P.; WYSE TECHNOLOGY L.L.C.; EMC CORPORATION
Reel/Frame 058297/0427 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Oct 15, 2019
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 050724/0466 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Nov 23, 2016
From: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; WYSE TECHNOLOGY L.L.C.; EMC CORPORATION
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 040679/0386 →
SECURITY INTEREST Recorded Nov 16, 2016
From: DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; WYSE TECHNOLOGY L.L.C.; EMC CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 040633/0799 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2016
From: GOUD, V. MALLIKARJUN; MUTNURY, BHYRAV M.
To: DELL PRODUCTS, LP
Reel/Frame 039679/0469 →
Continuity (1)
Related Publication 20180063944A1 · Mar 1, 2018