Memory system

1. A memory system comprising:

a semiconductor storage device including a plurality of blocks; and

a controller configured to

(i) instruct the semiconductor storage device to perform a read operation on data written to a block of the semiconductor storage device to determine whether or not to designate the block as a partial bad block if, after instructing the semiconductor storage device to perform a write operation on the block to write the data, status information read from the semiconductor storage device indicates that the write operation failed, and

(ii) designate the block as a partial bad block if read data that is returned from the semiconductor storage device in response to the instruction to perform the read operation has errors that are correctable, and as a bad block if read data that is returned from the semiconductor storage device in response to the instruction to perform the read operation has errors that are not correctable,

wherein the controller is configured to manage a partial bad block differently from a bad block,

wherein the controller is configured to instruct the semiconductor storage device to increase a threshold number of errors for determining that the write operation failed prior to a subsequent write operation on the block designated as a partial bad block, and

wherein the controller, after the subsequent write operation on the block designated as a partial bad block, sends a command for decreasing the threshold number of errors to the semiconductor storage device.

2. The system according to claim 1 , wherein

the controller includes an error checking and correcting (ECC) circuit, and

the errors in the read data are not correctable if the number of bits that need to be corrected is greater than an error-correcting capability of the ECC circuit.

3. The system according to claim 1 , wherein the controller designates the block as a partial bad block by instructing the semiconductor storage device to write first information into a management region of the semiconductor storage device and as a bad block by instructing the semiconductor storage device to write second information into the management region of the semiconductor storage device.

4. The system according to claim 1 ,

wherein the controller is configured to instruct the semiconductor storage device to perform a subsequent write operation on a block designated as a partial bad block, by instructing the semiconductor storage device to write target data of the subsequent write operation into the block and into another block that is not designated as a partial bad block or a bad block.

5. The system according to claim 4 , wherein the plurality of blocks are arranged in multiple planes and said another block is arranged in a plane that is different from a plane in which the partial bad block is arranged.

6. A memory system comprising:

a semiconductor storage device including a plurality of string units, each of the string units including a plurality of strings, and each of the strings including a plurality of serially-connected memory cells; and

a controller configured to

(i) instruct the semiconductor storage device to perform a read operation on data written to a string unit of the semiconductor storage device to determine whether or not to designate the string unit as a partial bad string unit if, after instructing the semiconductor storage device to perform a write operation on the string unit to write the data, status information read from the semiconductor storage device indicates that the write operation failed, and

(ii) designate the string unit as a partial bad string unit if read data that is returned from the semiconductor storage device in response to the instruction to perform the read operation has errors that are correctable, and as a bad string unit if read data that is returned from the semiconductor storage device in response to the instruction to perform the read operation has errors that are not correctable,

wherein the controller is configured to manage a partial bad string unit differently from a bad string unit,

wherein the controller is configured to instruct the semiconductor storage device to increase a threshold number of errors for determining that the write operation failed prior to a subsequent write operation on the string unit designated as a partial bad string unit, and

wherein the controller, after the subsequent write operation on the string unit designated as a partial bad string unit, sends a command for decreasing the threshold number of errors to the semiconductor storage device.

7. The system according to claim 6 , wherein

the controller includes an error checking and correcting (ECC) circuit, and

the errors in the read data are not correctable if the number of bits that need to be corrected is greater than an error-correcting capability of the ECC circuit.

8. The system according to claim 6 , wherein the controller designates the string unit as a partial bad string unit by instructing the semiconductor storage device to write first information into a management region of the semiconductor storage device and as a bad string unit by instructing the semiconductor storage device to write second information into the management region of the semiconductor storage device.

9. The system according to claim 6 ,

wherein the controller is configured to instruct the semiconductor storage device to perform a subsequent write operation on a string unit designated as a partial bad string unit, by instructing the semiconductor storage device to write target data of the subsequent write operation into the string unit and into another string unit that is not designated as a partial bad string unit or a bad string unit.

10. The system according to claim 9 , wherein the plurality of blocks are arranged in multiple planes and said another string unit is arranged in a plane that is different from a plane in which the partial bad string unit is arranged.

11. A method of managing blocks of memory cells of a semiconductor storage device as a normal block, a partial bad block, and a bad block, wherein a block represents a group of memory cells that are erased as a unit, comprising:

instructing the semiconductor storage device to perform a write operation on a block of memory cells;

reading status information from the semiconductor storage device to determine that the write operation failed;

upon determining that the write operation failed, instructing the semiconductor storage device to perform a read operation on data written pursuant to the write operation;

determining whether or not read data returned pursuant to the read operation contain errors that are correctable or not correctable;

designating the block as a partial bad block upon determining that the read data contain errors that are correctable;

designating the block as a bad block upon determining that the read data contain errors that are not correctable;

prior to a subsequent write operation on the block designated as a partial bad block, instructing the semiconductor storage device to increase a threshold number of errors for determining that the write operation failed; and

after the subsequent write operation on the block designated as a partial bad block, sending a command for decreasing the threshold number of errors to the semiconductor storage device.

12. The method according to claim 11 , further comprising:

instructing the semiconductor storage device to perform a subsequent write operation on a block designated as a partial bad block, by instructing the semiconductor storage device to write target data of the subsequent write operation into the block and into a normal block.

13. The method according to claim 12 , wherein the plurality of blocks are arranged in multiple planes and said normal block is arranged in a plane that is different from a plane in which the partial bad block is arranged.