IP Library Granted Patent US 10,476,958
Granted Patent B2
US 10,476,958 · App. 15/253,679 · Granted Nov 12, 2019

Hyper-converged flash array system

Inventor: Daisuke Hashimoto (Cupertino, CA)
Assignee: TOSHIBA MEMORY CORPORATION
H04L67/1097G06F3/061G06F3/0604G06F3/0659G06F3/0688G06F12/0246G06F3/067G06F3/0665G06F2212/1024G06F2212/7201
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Quick Facts
Patent No.
US 10,476,958
App. No.
15/253,679
Granted
Nov 12, 2019
Kind
B2
Abstract

A distributed system includes a plurality of storage systems and a network connecting the storage systems. Each storage system includes a host having a processor and a memory, and a storage device having a controller and a nonvolatile memory. When a first storage system receives, a second storage system, a write command, write data, and size information of the write data, the controller in the first storage system determines an address of the nonvolatile memory of the first storage system in which the write data are to be written, based on the write command and the size information, writes the write data in the nonvolatile memory associated with the address, and transmits the address to the second storage system, and the processor of the second storage system stores management data indicating correspondence between identification information of the write data and the address in the memory of the second storage system.

Claims (53)

1. A storage system comprising:

a housing;

a plurality of storage devices disposed in the housing, each of the storage devices including a nonvolatile semiconductor memory, a controller, and a communication interface; and

a host disposed in the housing, and including a processor, a memory in which mapping from an identification or a logical address of each data unit to a physical location of said each data unit is stored, an external network interface connectable to another storage system which is not disposed in said housing, through a storage system network, and an internal network controller connected to a communication interface of each of the storage devices, wherein

the processor of the host is configured to temporarily store, in the memory, an inbound access command that comes from said another storage system through the external network interface, and then transmit the stored inbound access command to one of the storage devices so as to cause a controller of the storage device to access a nonvolatile semiconductor memory thereof in accordance with the inbound access command, and

the inbound access command is issued by an operating system executed by said another storage system, which works with an operating system executed by the processor of the host in a coordinated manner.

2. The storage system according to claim 1 , wherein

when the inbound access command is a write command, the processor of the host temporarily stores also write data that comes through the storage system network in the memory, and then transmits the write data to said one of the storage devices so as to cause the controller thereof to write the write data in the nonvolatile semiconductor memory thereof.

3. The storage system according to claim 2 , wherein

the write command includes no mapping information about a location in which the write data are to be stored, and the controller of said one of the storage devices is configured to determine a physical location in which the write data are to be written and return to the host the physical location.

4. The storage system according to claim 3 , wherein

the processor of the host is further configured to transfer the physical location through the external network interface.

5. The storage system according to claim 1 , wherein

when the inbound access command is a read command, the processor of the host causes the controller of said one of the storage devices to read data from a physical location of the nonvolatile semiconductor memory thereof, the physical location being received in association with the read command, and transfers the read data to the storage system network through the external network interface.

6. The storage system according to claim 1 , wherein

when the inbound access command is an invalidate command, the processor of the host causes the controller of said one of the storage devices to invalidate data stored in a physical location of the nonvolatile semiconductor memory thereof, the physical location being received in association with the invalidate command, and returns a completion notification to the storage system network through the external network interface.

7. The storage system according to claim 1 , wherein

when the inbound access command is a copy command, the processor of the host causes the controller of said one of the storage devices to read data from a physical location of the nonvolatile semiconductor memory thereof, the physical location being received in association with the copy command, and transfers the read data towards another storage system designated by the copy command through the external network interface.

8. The storage system according to claim 1 , wherein

the processor of the host is further configured to generate an outbound access command and transmit the outbound access command towards another storage system connected to the storage system network, through the external network interface.

9. The storage system according to claim 8 , wherein

the mapping includes mapping information for data stored in another storage system connected to the storage system network.

10. The storage system according to claim 9 , wherein

the processor of the host determines a physical location in said another storage system to be accessed, by referring to the mapping when generating a read command, an invalidate command, or a copy command as the outbound access command, and does not determine the physical location when generating a write command as the outbound access command.

11. A method of operating a storage system connected to a storage system network connected to a plurality of storage systems, the storage system including a host externally connected to the storage system network and a plurality of storage devices internally connected to the host, the method comprising:

temporarily storing, in the host, an inbound access command that comes in from another storage system among the plurality of storage systems through the storage system network;

transmitting the stored inbound access command from the host to one of the storage devices; and

accessing, in said one of the storage devices, a nonvolatile semiconductor memory thereof in accordance with the inbound access command, wherein

the inbound access command is issued by an operating system executed by said another storage system, which works with an operating system executed by the host in a coordinated manner.

12. The method according to claim 11 , wherein

the inbound access command is a write command, the method further comprises:

temporarily storing, in the host, write data that comes in from said another storage system through the storage system network; and

transmitting the write data from the host to said one of the storage devices, wherein

the accessing includes writing the write data in the nonvolatile semiconductor memory thereof in accordance with the write command.

13. The method according to claim 12 , wherein

the write command includes no mapping information about a location in which the write data are to be stored, and

the accessing further includes determining a physical location in which the write data are to be written by said one of the storage devices, and returning to the host the physical location.

14. The method according to claim 13 , further comprising:

transferring the physical location from the host to said another storage system through the storage system network.

15. The method according to claim 11 , wherein

the inbound access command is a read command,

the accessing includes reading data from a physical location of the nonvolatile semiconductor memory thereof, the physical location coming in from said another storage system in association with the read command, and

the method further comprises transferring the read data from the host to said another storage system through the storage system network.

16. The method according to claim 11 , wherein

the inbound access command is an invalidate command,

the accessing includes invalidating data stored in a physical location of the nonvolatile semiconductor memory thereof, the physical location coming in from said another storage system in association with the invalidate command, and

the method further comprises returning a completion notification from the host to said another storage system through the storage system network.

17. The method according to claim 11 , wherein

the inbound access command is a copy command, and

the accessing includes reading data from a physical location of the nonvolatile semiconductor memory thereof, the physical location coming in from said another storage system in association with the copy command, and

the method further comprises transferring the read data from the host to another storage system designated by the copy command through the storage system network.

18. The method according to claim 11 , further comprising:

storing, in the host, mapping from an identification or a logical address of data stored in another storage system in the storage system network, to a physical location of the data in said another storage system.

Assignments (6)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2016
From: HASHIMOTO, DAISUKE
To: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Reel/Frame 039959/0530 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2016
From: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 039959/0572 →
Continuity (2)
Provisional Application 62268366 · Dec 16, 2015
Related Publication 20170180478A1 · Jun 22, 2017