Semiconductor memory device that randomizes data and randomizer thereof
View Patent ↗A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2 n−1 bytes, n being a number of registers included in the linear feedback shift register circuit.
1. A semiconductor memory device, comprising:
a NAND memory including a plurality of blocks, each of which is a unit of data erasing; and
a controller configured to
select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written,
set a value corresponding to the selected initial value to a linear feedback shift register circuit,
randomize the data using an output value of the linear feedback shift register circuit, and
write the randomized data to the address of the NAND memory, wherein a size of each of the blocks S is smaller than 2 n−1 bytes, n being a number of registers included in the linear feedback shift register circuit.
2. The semiconductor memory device according to claim 1 , wherein
a number P of the initial values included in the group is a prime number and satisfies 2 n−1 /P >S.
3. The semiconductor memory device according to claim 1 , wherein
the controller maintains correspondence between the initial values and indices, each of which is associated with at least an address of the NAND memory, and selects the initial value by referring to the correspondence.
4. The semiconductor memory device according to claim 3 , wherein
the controller is configured to shift an index associated with the address of the NAND memory in which the data are to be written, and an initial value corresponding to the shifted index is selected by the controller.
5. The semiconductor memory device according to claim 3 , wherein
each of the block includes a plurality of pages, each of which is a unit of data writing, and
the controller is configured to change indices associated with addresses of the NAND memory, such that indices of consecutive pages become non-consecutive.
6. The semiconductor memory device according to claim 1 , wherein
a plurality of exclusive disjunctions (XOR) of two values output from different two of the registers of the linear feedback shift register circuit is output from the linear feedback shift register circuit, a number of the registers included in the linear feedback shift register circuit being greater than three, and
processing of each bit of the data using one of the exclusive disjunctions is carried out for randomization.
7. The semiconductor memory device according to claim 1 , wherein
the value set in the linear feedback shift register circuit is equal to the selected initial value.
8. The semiconductor memory device according to claim 1 , wherein
the value set in the linear feedback shift register circuit is a value obtained by processing the selected initial value with a mixing value.
9. The semiconductor memory device according to claim 1 , wherein
the output value of the linear feedback shift register circuit is calculated using a mixing value, and the data are randomized using the calculated value.
10. The semiconductor memory device according to claim 1 , wherein
the controller sets the value corresponding to the selected initial value to a plurality of linear feedback shift register circuits, and randomizes the data using a plurality of output values that is output from the plurality of linear feedback shift register circuits.