IP Library Granted Patent US 10,276,586
Granted Patent B2
US 10,276,586 · App. 15/254,014 · Granted Apr 30, 2019

Semiconductor device and method for manufacturing same

Inventors: Atsushi Murakoshi (Yokkaichi Mie, JP); Yasuhito Yoshimizu (Yokkaichi Mie, JP); Tomofumi Inoue (Yokkaichi Mie, JP); Tatsuya Kato (Yokkaichi Mie, JP); Yuta Watanabe (Yokkaichi Mie, JP); Fumitaka Arai (Yokkaichi Mie, JP)
Assignee: Toshiba Memory Corporation
H01L27/1157H01L27/11519H01L27/11521H01L27/11548H01L27/11556H01L27/11565H01L27/11575H01L27/11578H01L27/11582H01L29/4234H01L29/42324H01L29/42328H01L29/42332H01L29/42348H01L29/42352H01L29/66825H01L29/7926
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Quick Facts
Patent No.
US 10,276,586
App. No.
15/254,014
Granted
Apr 30, 2019
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween.

Claims (36)

1. A semiconductor device comprising:

a substrate;

a semiconductor layer that extends in a direction perpendicular to a major surface of the substrate;

a core layer disposed within the semiconductor layer;

a first insulating film disposed on the semiconductor layer;

an oxide film disposed on the first insulating film;

a first electrode layer disposed on the oxide film;

a second insulating film layer disposed on the first electrode layer;

a first charge trapping layer comprising a semiconductor material disposed on the second insulating film layer;

a second charge trapping layer comprising an insulating film, wherein the second charge trapping layer and the second insulating film layer surround the first charge trapping layer; and

a second electrode layer disposed on the second charge trapping layer.

2. The semiconductor device according to claim 1 ,

wherein the second charge trapping layer includes hafnium, silicon, oxygen, and nitrogen, and

a nitrogen composition ratio of the second charge trapping layer is greater than or equal to 10%.

3. The semiconductor device according to claim 2 ,

wherein the second insulating film is separated from the first insulating film by the first electrode layer.

4. The semiconductor device according to claim 3 ,

wherein the first charge trapping layer is separated from the first insulating film by the oxide film, the first electrode layer and the second insulating film.

5. The semiconductor device according to claim 1 ,

wherein the semiconductor layer further extends in a direction parallel to the major surface of the substrate.

6. The semiconductor device according to claim 1 , further comprising a first set and a second set;

wherein the first set comprises a first part of the first electrode layer, a first part of the first charge trapping layer, a first part of the second charge trapping layer, and a first part of the second electrode layer, wherein the first set is disposed on a first side surface of the semiconductor layer, and

wherein the second set comprises a second part of the first electrode layer, a second part of the first charge trapping layer, a second part of the second charge trapping layer, and a second part of the second electrode layer, wherein the second set is disposed on a second side surface of the semiconductor layer opposite the first side surface of the semiconductor layer, and the first set and the second set face each other.

7. The semiconductor device according to claim 1 ,

wherein the first charge trapping layer is separated from the first insulating film by the oxide film, the first electrode layer and the second insulating film.

8. The semiconductor device according to claim 1 ,

wherein the semiconductor layer further extends in a direction parallel to the major surface of the substrate.

9. The semiconductor device according to claim 1 , further comprising a first set and a second set;

wherein the first set comprises a first part of the first electrode layer, a first part of the first charge trapping layer, a first part of the second charge trapping layer, and a first part of the second electrode layer, wherein the first set is disposed on a first side surface of the semiconductor layer, and

wherein the second set comprises a second part of the first electrode layer, a second part of the first charge trapping layer, a second part of the second charge trapping layer, and a second part of the second electrode layer, wherein the second set is disposed on a second side surface of the semiconductor layer opposite the first side surface of the semiconductor layer, and the first set and the second set face each other.

10. The semiconductor device according to claim 1 , further comprising:

a first block insulating layer disposed on the second charge trapping layer; and

a second block insulating layer disposed on the first block insulating layer.

11. The semiconductor device according to claim 10 , wherein the second electrode layer is in contact with a side surface of the first block insulating layer perpendicular to the major surface of the substrate and a side surface of the second block insulating layer perpendicular to the major surface of the substrate.

12. The semiconductor device according to claim 10 , wherein the second electrode layer is in contact with an upper surface of the first block insulating layer parallel to the major surface of the substrate, a lower surface parallel to the major surface of the substrate of the first block insulating layer and a side surface perpendicular to the major surface of the substrate of the second block insulating layer.

13. The semiconductor device according to claim 10 , wherein the second electrode layer is in contact with an upper surface of the first block insulating layer parallel to the major surface of the substrate a lower surface of the first block insulating layer parallel to the major surface of the substrate, and a side surface of the second block insulating layer perpendicular to the major surface of the substrate.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2016
From: MURAKOSHI, ATSUSHI; YOSHIMIZU, YASUHITO; INOUE, TOMOFUMI; KATO, TATSUYA; WATANABE, YUTA; ARAI, FUMITAKA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 040327/0011 →
Priority Claims (1)
JP 2016-047426 · Mar 10, 2016 · national
Continuity (1)
Related Publication 20170263613A1 · Sep 14, 2017
Cited By (2)
US 12,507,415 US 12,520,567