Memory device and host device
According to one embodiment, a memory device includes a memory and a controller circuit. The memory holds first data and second data. The first data and the second data are results of monitoring state of the memory device. The first data and the second data include values indicating results of monitoring attributes common between these data. The values are updated according to operation status of the memory device. The controller circuit switches an object to be read from the memory between the first data and the second data.
1. A memory device comprising:
a memory to hold first data and second data that are results of monitoring state of the memory device, the first data and the second data including values indicating results of monitoring attributes common between these data, the values being updated according to operation status of the memory device; and
a controller circuit that switches an object to be read from the memory between the first data and the second data,
wherein the controller circuit, in response to a received reset request, resets second data designated based on access information,
the controller circuit disables resetting the first data according to the received reset request, and
the memory holds the first data that represents the results of monitoring state of the memory device during a total period from production or shipment of the memory device.
2. The memory device according to claim 1 , wherein the access information is registered in the memory device, and
the controller circuit, according to a read request, reads data designated based on the access information out of the first data and the second data.
3. The memory device according to claim 2 , wherein the controller circuit receives a first command that is a request to register the access information and a second command that is a read request.
4. The memory device according to claim 2 , wherein the controller circuit receives a command that is a read request including an instruction to register the access information.
5. The memory device according to claim 2 , wherein the memory holds a plurality of second data, the plurality of second data includes values indicating results of monitoring attributes common between these data, and
the access information that designates one of the first data and the plurality of second data is registered in the memory device.
6. The memory device according to claim 1 , wherein the access information is registered in the memory device.
7. The memory device according to claim 1 , wherein if the access information designating the first data is registered, the controller circuit prohibits resetting according to the reset request.
8. The memory device according to claim 1 , wherein the controller circuit receives a first command that is a request to register the access information and a second command that is a reset request.
9. The memory device according to claim 1 , wherein the controller circuit receives a command that is a reset request including an instruction to register the access information.
10. The memory device according to claim 1 , wherein the memory holds a plurality of second data, the plurality of second data include values indicating results of monitoring attributes common between these data, and
the access information that designates one of the plurality of second data is registered in the memory device.
11. A host device which is connectable to a memory device that holds first data and second data that are results of monitoring state of the memory device, the first data and the second data including values indicating results of monitoring attributes common between these data, the values being updated according to operation status of the memory device, the host device comprising:
a controller circuit that issues requests to read the first data and the second data and reads either the first data or the second data based on access information registered in the memory device,
wherein the controller circuit issues a reset request to have the memory device reset the second data designated based on the access information registered in the memory device,
if the access information designating the first data is registered in the memory device, the memory device resetting according to the reset request is prohibited, and
the first data represents the results of monitoring state of the memory device during a total period from production or shipment of the memory device.
12. The host device according to claim 11 , wherein the controller circuit issues a read request and receives data designated based on the access information out of the first data and the second data.
13. The host device according to claim 12 , wherein the controller circuit issues a first command that is a request to register the access information and a second command that is a read request.
14. The host device according to claim 12 , wherein the controller circuit issues a command that is a read request including an instruction to register the access information.
15. The host device according to claim 11 , wherein the controller circuit issues a request to register the access information that designates one of the first data and a plurality of second data, and the plurality of second data includes values indicating results of monitoring attributes common between these data.
16. The host device according to claim 11 , wherein the controller circuit issues a first command that is a request to register the access information and a second command that is a reset request.
17. The host device according to claim 11 , wherein the controller circuit issues a command that is a reset request including an instruction to register the access information.