High density substrate routing in BBUL package

Inventors: Weng Hong Teh (Phoenix, AZ); Chia-Pin Chiu (Tempe, AZ)

Assignee: Intel Corporation

H01L24/25 H01L23/3107 H01L23/3114 H01L23/50 H01L23/5389 H01L24/19 H01L24/24 H01L25/16 H01L25/18 H01L21/568 H01L23/3128 H01L2224/04105 H01L2224/12105 H01L2224/16227 H01L2224/2501 H01L2224/2505 H01L2224/255 H01L2224/2512 H01L2224/73209 H01L2224/81005 H01L2224/92133 H01L2924/10253 H01L2924/12042 H01L2924/141 H01L2924/1431 H01L2924/1461 H01L2924/15192 H01L2924/15747 H01L2924/18161 H01L2924/18162

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Quick Facts

Patent No.: US 9,929,119
App. No.: 15/255,351
Granted: Mar 27, 2018
Kind: B2

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Abstract

Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Claims (28)

1. A device comprising:

a substrate;

a first die on or at least partially in a first layer of the substrate, the first die including a first plurality of high density interconnect pads on a first side thereof;

a second die on or at least partially in the first layer of the substrate, the second die including a second plurality of high density interconnect pads; and

a high density interconnect element embedded in the substrate in a different layer than the first layer, the high density interconnect element including a third plurality of high density interconnect pads on a side facing the first side of the first die, one or more interconnect pads of the third plurality of high density interconnect pads electrically coupled to an interconnect pad of the first and second plurality of high density interconnect pads.

2. The device of claim 1 , further comprising at least one buildup layer formed over the high density interconnect element.

3. The device of claim 2 , wherein the high density interconnect element is one of a silicon die interconnect bridge and a glass die interconnect bridge.

4. The device of claim 3 , wherein the substrate is a Bumpless Buildup Layer (BBUL) substrate.

5. The device of claim 4 , further comprising a first adhesive on a non-active surface of the first die.

6. The of device of claim 5 , further comprising a second adhesive on a non-active surface of the second die.

7. The device of claim 6 , wherein the substrate includes low density interconnect routing therein that includes a power bus or a ground bus.

8. The device of claim 7 , wherein the first and second dies include a first and second plurality of low density interconnect pads, respectively, the first and second plurality of low density interconnect pads electrically coupled to the low density interconnect routing, the first and second plurality of low density interconnect pads includes up to about twenty-three pads per millimeter per layer.

9. The device of claim 8 , wherein the first, second, and third high density interconnect pads include greater than twenty-three pads per millimeter per layer and less than about two hundred fifty pads per millimeter per layer.

10. The device of claim 9 , wherein an interconnect pad of the first plurality of high density interconnect pads is electrically connected to a first interconnect pad of the third plurality of high density interconnect pads, an interconnect pad of the second plurality of high density interconnect pads is electrically connected to a second interconnect pad of the third plurality of high density interconnect pads, and the first interconnect pad of the third plurality of high density interconnect pads is electrically connected to the second interconnect pad of the third plurality of high density interconnect pads by a trace.

11. The device of claim 10 , wherein the interconnect pad of the first plurality of high density interconnect pads is electrically connected to a data line of the first die.

12. The device of claim 11 , wherein the first die is a logic die and the second die is an analog die.

13. A device including:

a substrate including low density interconnect routing therein;

a first die on or at least partially embedded in the substrate, the first die including a first plurality of high density interconnect pads and a first plurality of low density interconnect pads, the first plurality of low density interconnect pads electrically coupled to the low density interconnect routing;

a second die on or at least partially embedded in the substrate, the second die including a second plurality of high density interconnect pads and a second plurality of low density interconnect pads, the second plurality of low density interconnect pads electrically coupled to the low density interconnect routing; and

a high density interconnect element at least partially embedded in the substrate, the high density interconnect element including a third plurality of high density interconnect pads, each interconnect pad of the third plurality of high density interconnect pads electrically coupled to an interconnect pad of each of the first plurality of high density interconnect pads and electrically coupled to an interconnect pad of the second plurality of high density interconnect pads, wherein the high density interconnect element is a chip.

14. The device of claim 13 , wherein the first die is a logic die and the second die is an analog die.

15. The device of claim 13 , wherein the high density interconnect element is one of a silicon die interconnect bridge and a glass die interconnect bridge.

16. The device of claim 13 , wherein the low density interconnect routing includes a power bus or a ground bus.

17. The device of claim 13 , wherein the first and second low density interconnect pads including up to about twenty-three pads per millimeter per layer.

18. The device of claim 13 , wherein the first, second, and third high density interconnect pads include between about twenty-three pads per millimeter per layer and about two hundred fifty pads per millimeter per layer.

19. The device of claim 13 , further comprising a first adhesive on non-active side of the first die.

20. The device of claim 13 , further comprising a second adhesive on a non-active side of the second die.

Continuity (4)

Continuation 14922425 · Oct 26, 2015

Continuation 14663689 · Mar 20, 2015

Division 13707159 · Dec 6, 2012

Related Publication 20170053887A1 · Feb 23, 2017