Data communication system and data receiving device

1. A data communication system comprising:

a data transmitting device that transmits a test pattern; and

a data receiving device that receives the test pattern, wherein

the test pattern includes a data test pattern and a clock test pattern, the data test pattern including data bit sequence, the clock test pattern including clock bit, the data bit sequence having N (N is a positive integer) bits, the clock bit having one bit,

the data receiving device receives the N bits of the data bit sequence and the one bit of the clock bit in parallel, and

the data receiving device includes:

N first comparators corresponding to the N bits of the data bit sequence, the N first comparators comparing each of the N bits of the data bit sequence with a first threshold voltage in parallel to determine whether each of the N bits of the data bit sequence is at High level or Low level;

a second comparator corresponding to the one bit of the clock bit, the second comparator comparing the one bit of the clock bit with a second threshold voltage to determine whether the clock bit is at High level or Low level;

N flip-flops that hold the N bits of the data bit sequence in synchronization with the one bit of the clock bit; and

a comparison circuit that receives the held N bits of the data bit sequence in parallel as the data test pattern and that compares the data test pattern with an expected value.

2. The data communication system of claim 1 , wherein

the data receiving device further includes:

a selection circuit that selects, from a plural candidate values, a value of the first threshold voltage and a value of the second threshold voltage as a common value, based on a result of the comparison between the data test pattern and the expected value;

a control circuit that controls both of the value of the first threshold voltage for the N first comparators and the value of the second threshold voltage for the second comparator, to the selected common value; and

a memory that holds the expected value corresponding to the data test pattern.

3. The data communication system of claim 2 , wherein

the data receiving device further includes:

a generator that generates the common value for the fl threshold voltage and the second threshold voltage to provide the N first comparators and the second comparator with the common value in parallel.

4. The data communication system of claim 1 , wherein

the data receiving device transmits a test pattern request command to the data transmitting device before receipt of the test pattern, or

the data transmitting device transmits a test pattern transmission command to the data receiving device before transmission of the test pattern.

5. The data communication system of claim 2 , wherein

when mapping information includes plural points obtained by associating the plural candidate values of the common value with plural candidate patterns of the data bit sequence and the mapping information has within the plural points a certain range of points where the data test pattern matches with the expected value corresponding to the data bit sequence, the selection circuit selects the common value corresponding to a middle point in the certain range of points.

6. The data communication system of claim 2 , wherein

the data receiving device stores the selected common value, and uses the common value stored at a time of subsequently receiving data to determine whether the data is at High level or Low level.

7. The data communication system of claim 1 , wherein

the data receiving device further includes:

a selection circuit that selects, from a plural candidate values, a value of the first threshold voltage and a value of the second threshold voltage as different values, based on a result of the comparison between the data test pattern and the expected value;

a control circuit that controls the value of the first threshold voltage for the N first comparators to a first value and the value of the second threshold voltage for the second comparator to a second value different from the first value; and

a memory that holds the expected value corresponding to the data test pattern.

8. The data communication system of claim 1 , wherein

the data transmitting device is a host device and

the data receiving device is a memory device.

9. The data communication system of claim 8 , wherein

the host device is an embedded Multi Media Card (eMMC) host and

the data receiving device is an eMMC memory.

10. The data communication system of claim 1 , wherein

the data transmitting device is a NAND flash memory and

the data receiving device is a memory controller.

11. A data receiving device that receives a test pattern, wherein

the test pattern includes a data test pattern and a clock test pattern, the data test pattern including data bit sequence, the clock test pattern including clock bit, the data bit sequence having N (N is a positive integer) bits, the clock bit having one bit,

the data receiving device receives the N bits of the data bit sequence and the one bit of the clock bit in parallel, and

the data receiving device includes:

N first comparators corresponding to the N bits of the data bit sequence, the N first comparators comparing each of the N bits of the data bit sequence with a first threshold voltage in parallel to determine whether each of the N bits of the data bit sequence is at High level or Low level;

a second comparator corresponding to the one bit of the clock bit, the second comparator comparing the one bit of the clock bit with a second threshold voltage to determine whether the one bit of the clock bit is at High level or Low level;

N flip-flops that hold the N bits of the data bit sequence in synchronization with the one bit of the clock bit; and

a comparison circuit that receives the held N bits of the data bit sequence in parallel as the data test pattern and that compares the data test pattern with an expected value.

12. The data receiving device of claim 11 ,

further including:

a selection circuit that selects, from a plural candidate values, a value of the first threshold voltage and a value of the second threshold voltage as a common value, based on a result of the comparison between the data test pattern and the expected value;

a control circuit that controls both of the value of the first threshold voltage for the N first comparators and the value of the second threshold voltage for the second comparator to the selected common value; and

a memory that holds the expected value corresponding to the data test pattern.

13. The data receiving device of claim 12 ,

further including:

a generator that generates the common value for the first threshold voltage and the second threshold voltage to provide the N first comparators and the second comparator with the common value in parallel.

14. The data receiving device of claim 11 , transmitting a test pattern request command before receipt of the test pattern.

15. The data receiving device of claim 12 , wherein,

when mapping information includes plural points obtained by associating the plural candidate values of the common value with plural candidate patterns of the data bit sequence and the mapping information has within the plural points a certain range of points where the data test pattern matches with the expected value corresponding to the data bit sequence, the selection circuit selects the common value corresponding to a middle point in the certain range of points.

16. The data receiving device of claim 12 , storing the selected common value and using the common value stored at a time of subsequently receiving data to determine whether the data is at High level or Low level.

17. The data receiving device of claim 11 , further including:

a selection circuit that selects, from a plural candidate values, a value of the first threshold voltage and a value of the second threshold voltage as different values, based on a result of the comparison between the data test pattern and the expected value;

a control circuit that controls the value of the first threshold voltage for the N first comparators to a first value and the value of the second threshold voltage for the second comparator to a second value different from the first value; and

a memory that holds the expected value corresponding to the data test pattern.

18. The data receiving device of claim 11 , wherein

the data receiving device is a memory device.

19. The data receiving device of claim 18 , wherein

the data receiving device is an embedded Multi Media Card (eMMC) memory.

20. The data receiving device of claim 11 , wherein

the data receiving device is a memory controller that controls a NAND flash memory.