Controller and memory system
According to one embodiment, a controller determines a write operation, when a write request to a memory, a write address and data are received, by comparing an amount of use of a write buffer and a threshold for determining a change of a write operation to the memory. The memory is capable of overwriting first data to second data at an identical physical address of the memory. By the determined write operation, the received data is written to the received write address of the memory.
1. A controller comprising:
a host interface circuit configured to receive a write request to a memory, a write address and data;
a determination circuit configured to determine a write operation in accordance with an amount of use of the data to be written of a write buffer, the write buffer storing the data received by the host interface circuit; and
a change circuit configured to change a notification method to a host in accordance with the write operation determined by the determination circuit,
wherein the changed notification method to the host includes returning a response to the host when the amount of use of the data to be written of the write buffer is less than a threshold, and the controller further comprises a write circuit configured to output the received write request to the memory, the received write address and the received data to the memory, and
wherein the received write request to the memory, the received write address and a size of the received data are stored in a nonvolatile memory when the amount of use of the data to be written of the write buffer is equal to or more than the threshold and an interruption of a power supply to the controller is detected.
2. The controller of claim 1 , wherein the threshold is set to be a data amount that the received data in the write buffer is transferable to the memory even when a power supply to the controller is interrupted.
3. The controller of claim 1 , wherein the memory is capable of overwriting first data with second data at an identical physical address of the memory.
4. The controller of claim 1 , wherein the write circuit is configured to write a predetermined value in a predetermined area of the memory, and
wherein when restoration from power-down of the controller has occurred, the controller is configured to:
read the value of the predetermined area;
detect whether the written value is consistent with the read value or not;
determine the threshold based on a result of the detection where the written value is consistent with the read value.