IP Library Granted Patent US 9,911,753
Granted Patent B2
US 9,911,753 · App. 15/257,138 · Granted Mar 6, 2018

Semiconductor device and method for manufacturing semiconductor device

Inventors: Masayuki Kitamura (Mie, JP); Atsuko Sakata (Mie, JP); Satoshi Wakatsuki (Mie, JP); Takeshi Ishizaki (Aichi, JP); Daisuke Ikeno (Mie, JP); Tomotaka Ariga (Mie, JP)
Assignee: Toshiba Memory Corporation
H01L27/11582H01L21/486H01L23/49827H01L27/11556H01L29/66833H01L29/7926
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,911,753
App. No.
15/257,138
Granted
Mar 6, 2018
Kind
B2
Abstract

According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.

Claims (24)

1. A semiconductor device, comprising:

a substrate;

a stacked body provided above the substrate, the stacked body including a plurality of electrode layers stacked with an air gap interposed, the stacked body including a stairstep portion in which the electrode layers are arranged in a stairstep configuration with a difference in levels in a first direction;

a first columnar portion including a semiconductor body and a stacked film, the semiconductor body extending in a stacking direction through the stacked body, the stacked film including a charge storage portion and being provided between the semiconductor body and the electrode layers;

an insulating layer provided above the stairstep portion;

a first cover film provided between the stairstep portion and the insulating layer, the first cover film being of a material different from the insulating layer, the first cover film covering edges in the first direction of the electrode layers of the stairstep portion, and plugging the air gap between the electrode layers of the stairstep portion;

a separation portion extending in the stacking direction and the first direction, and dividing the stacked body and the insulating layer in a second direction intersecting the first direction; and

a second cover film provided at a side surface of the insulating layer on the separation portion side, the second cover film being of a material different from the insulating layer.

2. The semiconductor device according to claim 1 , wherein

one portion of the first cover film plugging the air gap is provided between a tip portion of one electrode layer of the stairstep portion on the edge side and another electrode layer under the tip portion, and

the tip portion of the one electrode layer is supported, via the one portion of the first cover film, on another electrode layer under the tip portion.

3. The semiconductor device according to claim 2 , further comprising a contact via contacting the one electrode layer of the stairstep portion and extending in the stacking direction through the insulating layer,

the one portion of the first cover film spreading to a region overlapping a lower end of the contact via.

4. The semiconductor device according to claim 1 , further comprising a contact via contacting one electrode layer of the stairstep portion and extending in the stacking direction through the insulating layer.

5. The semiconductor device according to claim 1 , wherein

the insulating layer is a silicon oxide layer, and

the first cover film and the second cover film are a silicon nitride film or a metal oxide film.

6. The semiconductor device according to claim 1 , wherein

the separation portion includes:

an interconnect portion; and

an insulating film provided between the interconnect portion and the second cover film, and between the interconnect portion and the stacked body.

7. The semiconductor device according to claim 1 , further comprising a third cover film provided on the insulating layer, the third cover film being of a material different from the insulating layer.

8. The semiconductor device according to claim 7 , further comprising a second columnar portion extending in the stacking direction through the stacked body of the stairstep portion, through the insulating layer above the stairstep portion, and through the first cover film between the stairstep portion and the insulating layer.

9. The semiconductor device according to claim 8 , wherein the third cover film covers an upper end of the second columnar portion.

Assignments (6)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 042910 FRAME 0321. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 042910/0321 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2016
From: KITAMURA, MASAYUKI; SAKATA, ATSUKO; WAKATSUKI, SATOSHI; ISHIZAKI, TAKESHI; IKENO, DAISUKE; ARIGA, TOMOTAKA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 039676/0875 →
Continuity (2)
Provisional Application 62279239 · Jan 15, 2016
Related Publication 20170207236A1 · Jul 20, 2017