IP Library Granted Patent US 9,720,870
Granted Patent B2
US 9,720,870 · App. 15/257,666 · Granted Aug 1, 2017

Semiconductor device and memory system

Inventors: Kunihiko Yamagishi (Yokohama, JP); Toshitada Saito (Yokohama, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
G06F13/4068G06F12/0246G06F13/385G06F13/40G06F13/4063G06F13/42G06F13/4282G06F2212/7201G06F2213/3804G06F2213/3854
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Quick Facts
Patent No.
US 9,720,870
App. No.
15/257,666
Granted
Aug 1, 2017
Kind
B2
Abstract

A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Claims (46)

1. A method of controlling a semiconductor memory by a controller circuit, the semiconductor memory capable of holding data, and the controller circuit capable of accessing the semiconductor memory based on a command from a host apparatus, the method comprising:

selecting one of a first symbol and a second symbol in a random order;

performing 8b/10b coding for the selected symbol; and

transmitting the 8b/10b coded symbol to the host apparatus,

wherein the first and second symbols indicate an idle state,

wherein the 8b/10b coded symbol is repeatedly transmitted to the host apparatus,

wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, and

wherein a symbol selected by the controller circuit has a running disparity different from that of a symbol which is most recently selected by the controller circuit.

2. The method according to claim 1 , wherein data to be transmitted from the controller to the host apparatus is scrambled, and the scrambled data is transmitted to the host apparatus.

3. The method according to claim 1 , wherein the controller circuit selects one of the first and second symbols according to a random number.

4. The method according to claim 1 , wherein the controller circuit transmits, to the host apparatus, the coded symbol and coded scramble data as one symbol set.

5. A method of controlling a semiconductor memory by a controller circuit, the semiconductor memory capable of holding data, and the controller circuit capable of accessing the semiconductor memory based on a command from a host apparatus, the method comprising:

selecting one of a first symbol and a second symbol in a random order;

selecting a third symbol which indicates a delimiter;

performing 8b/10b coding for the selected symbols; and

transmitting the 8b/10b coded symbols to the host apparatus,

wherein a symbol set including the 8b/10b coded one of the first and second symbols and the 8b/10b coded third symbol is repeatedly transmitted to the host apparatus,

wherein the symbol set is used to set up synchronization with the host apparatus,

wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, and

wherein a symbol selected by the controller circuit has a running disparity different from that of a symbol which is most recently selected by the controller circuit.

6. The method according to claim 5 , wherein data to be transmitted from the controller to the host apparatus is scrambled, and the scrambled data is transmitted to the host apparatus.

7. The method according to claim 5 , wherein the controller circuit selects one of the first and second symbols according to a random number.

8. The method according to claim 5 , wherein the controller circuit transmits, to the host apparatus, the coded symbol and coded scramble data as one symbol set.

9. A method of controlling a semiconductor memory by a controller circuit, the semiconductor memory capable of holding data, and the controller circuit capable of accessing the semiconductor memory based on a command from a host apparatus, the method comprising:

selecting one of a first symbol and a second symbol in a random order;

performing 8b/10b coding for the selected symbol; and

transmitting the 8b/10b coded symbol to the host apparatus,

wherein the first and second symbols indicate an idle state,

wherein the 8b/10b coded symbol is repeatedly transmitted to the host apparatus,

wherein one of the first and second symbols is a symbol in which running disparity becomes ±0, and

wherein a symbol selected by the controller circuit has a running disparity different from that of a symbol which is most recently selected by the controller circuit.

10. The method according to claim 9 , wherein data to be transmitted from the controller to the host apparatus is scrambled, and the scrambled data is transmitted to the host apparatus.

11. The method according to claim 9 , wherein the controller circuit selects one of the first and second symbols according to a random number.

12. The method according to claim 9 , wherein the controller circuit transmits, to the host apparatus, the coded symbol and coded scramble data as one symbol set.

13. A method of controlling a semiconductor memory by a controller circuit, the semiconductor memory capable of holding data, and the controller circuit capable of accessing the semiconductor memory based on a command from a host apparatus, the method comprising:

selecting one of a first symbol and a second symbol in a random order;

selecting a third symbol which indicates a delimiter;

performing 8b/10b coding for the selected symbols; and

transmitting 8b/10b coded symbols to the host apparatus,

wherein a symbol set including the 8b/10b coded one of the first and second symbols and the 8b/10b coded third symbol is repeatedly transmitted to the host apparatus,

wherein the symbol set is used to set up synchronization with the host apparatus,

wherein one of the first and second symbols is a symbol in which running disparity becomes ±0, and

wherein a symbol selected by the controller circuit has a running disparity different from that of a symbol which is most recently selected by the controller circuit.

14. The method according to claim 13 , wherein data to be transmitted from the controller to the host apparatus is scrambled, and the scrambled data is transmitted to the host apparatus.

15. The method according to claim 13 , wherein the controller circuit selects one of the first and second symbols according to a random number.

16. The method according to claim 13 , wherein the controller circuit transmits, to the host apparatus, the coded symbol and coded scramble data as one symbol set.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043328/0388 →
Priority Claims (1)
JP 2009-279719 · Dec 9, 2009 · national
Continuity (4)
Continuation 14797970 · Jul 13, 2015
Continuation 14292180 · May 30, 2014
Continuation 13514736
Related Publication 20160371217A1 · Dec 22, 2016