INFORMATION PROCESSING APPARATUS
According to one embodiment, an information processing apparatus includes a host device, a memory system and a power supply circuit. The host device includes a volatile first memory and a first control circuit. The memory system includes a non-volatile second memory in which user data is stored and a second control circuit. The second control circuit executes transfer of the user data between the host device and the second memory. The first memory includes an area used by the second control circuit. The second control circuit uses the area as a buffer for the transfer. The first control circuit causes the power supply circuit to start and stop the power supply to the memory system. The first control circuit accesses, while the power supply to the memory system is stopped, the buffer.
1 . An information processing apparatus comprising:
a host device including a volatile first memory and a first control circuit;
a memory system including a non-volatile second memory in which user data is stored and a second control circuit that executes transfer of the user data between the host device and the second memory; and
a power supply circuit, wherein
the first memory includes an area, the area being used by the second control circuit,
the second control circuit uses the area as a buffer for the transfer, and
the first control circuit causes the power supply circuit to start and stop the power supply to the memory system and accesses, while the power supply to the memory system is stopped, the buffer.
2 . The information processing apparatus according to claim 1 , wherein
the second control circuit stores, to the area, tag information for identifying first user data, the first user data being user data stored in the buffer, and
the first control circuit determines, while the power supply to the memory system is stopped, whether second user data is the first user data based on the tag information, the second user data being user data to be read.
3 . The information processing apparatus according to claim 2 , wherein
in a case where the second user data is the first user data, the first control circuit reads the second user data from the buffer.
4 . The information processing apparatus according to claim 2 , wherein
in a case where the second user data is not the first user data, the first control circuit causes the power supply circuit to start the power supply to the memory system and transmits, to the memory system, a read command for reading the second user data.
5 . The information processing apparatus according to claim 4 , wherein
the second control circuit reads the second user data from the second memory in response to the read command, and transmits the read second user data to the host device.
6 . The information processing apparatus according to claim 1 , wherein
the second control circuit does not delete the buffer from the area, when the power supply circuit stops the power supply to the memory system.
7 . The information processing apparatus according to claim 2 , wherein
the tag information indicates correspondence between the first user data and a logical address of the first user data, and
the first control circuit determines whether the second user data is the first user data by searching for the tag information using a logical address of the second user data.
8 . The information processing apparatus according to claim 1 , wherein
the second control circuit stores, to the area, tag information for identifying first user data, the first user data being user data stored in the buffer, and
the first control circuit determines, while the power supply to the memory system is stopped, whether the buffer is available for storing second user data based on the tag information, the second user data being user data to be written.
9 . The information processing apparatus according to claim 8 , wherein
in a case where the buffer is available, the first control circuit writes the second user data to the buffer.
10 . The information processing apparatus according to claim 8 , wherein
in a case where the buffer is not available, the first control circuit causes the power supply circuit to start the power supply to the memory system and transmits, to the memory system, a write command.
11 . The information processing apparatus according to claim 8 , wherein
the tag information indicates correspondence between the first user data and a logical address of the first user data, and
the first control circuit
determines that the buffer is available, in a case where the logical address of the second user data is same as the logical address of the first user data, and
determines that the buffer is not available, in a case where the logical address of the second user data is not same as the logical address of the first user data.
12 . An information processing apparatus comprising:
a host device including a volatile first memory and a first control circuit;
a memory system including a non-volatile second memory in which user data is stored, and a second control circuit that executes transfer of the user data between the host device and the second memory;
a first power supply circuit that starts and stops power supply to the second control circuit; and
a second power supply circuit that starts and stops power supply to the second memory, wherein
the first memory includes an area, the area being used by the second control circuit,
the second circuit uses the area as a buffer for the transfer, and
the first control circuit causes the first power supply circuit to start the power supply to the second control circuit and transmits an access command to the memory system, and the second control circuit, while the power supply to the second memory is stopped, processes the access command by using the buffer.
13 . The information processing apparatus according to claim 12 , wherein
the access command is a read command for reading first user data, the first user data being user data to be read, and
the second control circuit stores, to the area, tag information for identifying second user data, the second user data being user data stored in the buffer, and determines, while the power supply to the second memory is stopped, whether the first user data is the second user data based on the tag information.
14 . The information processing apparatus according to claim 13 , wherein
in a case where the first user data is the second user data, the second control circuit reads the first user data from the buffer.
15 . The information processing apparatus according to claim 13 , wherein
in a case where the first user data is the second user data, the second control circuit causes the second power supply circuit to start the power supply to the second memory and reads the first user data from the second memory.
16 . The information processing apparatus according to claim 12 , wherein
the second control circuit does not delete the buffer from the area when the first power supply circuit and the second power supply circuit stop the power supply.
17 . The information processing apparatus according to claim 13 , wherein
the tag information indicates correspondence between the second user data and a logical address of the second user data, and
the second control circuit determines whether the first user data is the second user data by searching for the tag information using a logical address of the first user data.
18 . The information processing apparatus according to claim 12 , wherein
the access command is a write command for writing first user data, the first user data being user data to be written,
the second circuit stores, to the area, tag information for identifying second user data, the second user data being user data stored in the buffer, and
the second circuit determines, while the power supply to the second memory is stopped, whether the buffer is available for storing the first user data based on the tag information.
19 . The information processing apparatus according to claim 18 , wherein
in a case where the buffer is available, the second circuit writes the first user data to the buffer.
20 . The information processing apparatus according to claim 18 , wherein
in a case where the buffer is not available, the second circuit causes the second power supply circuit to start the power supply to the second memory and moves the second user data from the buffer to the second memory.