IP Library Granted Patent US 9,712,053
Granted Patent B2
US 9,712,053 · App. 15/258,779 · Granted Jul 18, 2017

DC-DC converter with digital current sensing

Inventors: Hassan Ihs (San Diego, CA); Taner Dosluoglu (New York, NY)
Assignee: Endura Technologies LLC
H02M3/157G05F1/575H02M1/08H02M3/156H02M3/158H02M3/155H02M2001/0009
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Quick Facts
Patent No.
US 9,712,053
App. No.
15/258,779
Granted
Jul 18, 2017
Kind
B2
Abstract

A regulated DC-DC switching converter includes a bypass mode in which ends of an output inductor are coupled together. Circuitry determines output capacitor current and load current components of output inductor current during operation of the switching converter, for use in controlling switching operations.

Claims (19)

1. A method of determining output inductor current for a DC-DC switching regulator including a bypass switch coupling ends of the output inductor and an output capacitor, the output inductor having one end coupled to a node between a high side switch and a low side switch coupled in series and another end coupled to the output capacitor, comprising:

digitizing a first voltage of a node between the output inductor and the output capacitor at a first time to obtain a first digital output capacitor voltage;

storing an indication of the first digital output capacitor voltage;

digitizing a second voltage of the node between the output inductor and the output capacitor at a second time to obtain a second digital output capacitor voltage;

determining a first value indicative of output capacitor current based on the indication of the first digital output capacitor voltage and the second digital output capacitor voltage;

digitizing a third voltage of the node between the output inductor and the output capacitor at a third time to obtain a third digital output capacitor voltage;

storing an indication of the third digital output capacitor voltage;

digitizing a fourth voltage of the node between the output inductor and the output capacitor at a fourth time to obtain a fourth digital output capacitor voltage;

determining a second value indicative of output capacitor current based on the indication of the third digital output capacitor voltage and the fourth digital output capacitor voltage; and

determining an indication of output inductor current based on the first value indicative of output capacitor current and the second value indicative of output capacitor current to obtain an indication of output inductor current;

wherein the bypass switch is open at the first time and the second time and the bypass switch is closed at the third time and the fourth time.

2. The method of claim 1 , wherein a difference between the first time and the second time is equal to a difference between the third time and the fourth time.

3. The method of claim 1 , wherein the indication of the first digital output capacitor current and the indication of the second digital output capacitor current are stored as digital values in a memory.

4. The method of claim 1 , further comprising determining if the bypass switch has been closed within a first predetermined period of time, and closing the bypass switch for a second predetermined period of time if the bypass switch has not been closed within the first predetermined period of time.

5. The method of claim 1 , wherein digitization of the first, second, third, and fourth voltages of the node between the output indicator and the output capacitor are performed using an analog to digital converter.

6. The method of claim 1 , wherein the indication of output inductor current is determined by summing the first value indicative of output capacitor current and the second value indicative of output capacitor current.

7. The method of claim 6 , wherein the summing the first value indicative of output capacitor current and the second value indicative of output capacitor current is performed by adder circuitry.

8. The method of claim 5 , wherein the analog to digital converter provides greater than eight bits of meaningful output across a range within two percent of expected voltages of the node between the output inductor and the output capacitor during voltage regulation of power.

9. The method of claim 5 , wherein the analog to digital converter comprises at least ten comparators.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2023
From: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD.
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 063424/0226 →
CHANGE OF NAME Recorded Mar 29, 2022
From: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO., LTD.
To: CHAOYANG SEMICONDUCTOR (SHANGHAI) CO., LTD
Reel/Frame 061088/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2018
From: ENDURA IP HOLDINGS LTD.
To: ENDURTECH (HONG KONG) LIMITED
Reel/Frame 045987/0673 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2018
From: ENDURTECH (HONG KONG) LIMITED
To: CHAOYANG SEMICONDUCTOR JIANGYIN TECHNOLOGY CO. LTD.
Reel/Frame 045989/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2018
From: ENDURA TECHNOLOGIES LLC
To: ENDURA IP HOLDINGS LTD.
Reel/Frame 045931/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2016
From: IHS, HASSAN; DOSLUOGLU, TANER
To: ENDURA TECHNOLOGIES LLC
Reel/Frame 039805/0074 →
Continuity (3)
Continuation 14593987 · Jan 9, 2015
Provisional Application 62086038 · Dec 1, 2014
Related Publication 20160380535A1 · Dec 29, 2016