IP Library Granted Patent US 9,858,973
Granted Patent B2
US 9,858,973 · App. 15/261,771 · Granted Jan 2, 2018

Variable change memory and the writing method of the same

Inventors: Shintaro Sakai (Seoul, KR); Masahiko Nakayama (Kawasaki Kanagawa, JP); Katsuyuki Fujita (Nishitokyo Tokyo, JP); Hiromi Noro (Seoul, KR)
Assignee: TOSHIBA MEMORY CORPORATION
G11C11/161G11C11/1655G11C11/1673G11C11/1675G11C11/1693G11C13/0026G11C13/0061G11C13/0069H01L27/228H01L43/08H01L43/10G11C2013/0076G11C2213/78G11C2213/79
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Quick Facts
Patent No.
US 9,858,973
App. No.
15/261,771
Granted
Jan 2, 2018
Kind
B2
Abstract

According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.

Claims (12)

1. A writing method of a memory having a memory cell including an MTJ element, comprising:

applying a voltage which oscillates at a predetermined period to the MTJ element; and

applying, to the MTJ element, a predetermined voltage higher than a peak voltage of the voltage which oscillates at the predetermined period after the voltage which oscillates at the predetermined period is applied to the MTJ element.

2. The writing method of the memory according to claim 1 , wherein:

one end of the MTJ element is connected to a bit line,

the other end of the MTJ element is connected to one end of a select transistor,

the other end of the select transistor is connected to a source line, and

the voltage which oscillates at the predetermined period and the predetermined voltage are applied from a side of the bit line to the MTJ element.

3. The writing method of the memory according to claim 1 , wherein the predetermined period is not less than 1 GHz.

4. The writing method of the memory according to claim 1 , wherein the predetermined period is not less than 10 GHz.

5. The writing method of the memory according to claim 1 , wherein an application time of the voltage which oscillates at the predetermined period is shorter than the application time of the predetermined voltage.

6. The writing method of the memory according to claim 5 , wherein the voltage that oscillates at the predetermined period is superimposed on the predetermined voltage at a start of application of the predetermined voltage.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0382 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2016
From: SAKAI, SHINTARO; NAKAYAMA, MASAHIKO; FUJITA, KATSUYUKI; NORO, HIROMI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 040137/0078 →
Continuity (3)
Continuation PCTJP2014074755 · Sep 11, 2014
Provisional Application 61952649 · Mar 13, 2014
Related Publication 20160379697A1 · Dec 29, 2016