Cache memory and processor system
A cache memory has cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry, a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry, and a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code.
1. A cache memory comprising:
cache memory circuitry comprising a nonvolatile memory cell to store a data;
error correction circuitry to generate a redundancy code of the data stored in the nonvolatile memory cell;
a first redundancy code storage comprising a nonvolatile memory cell capable of storing the redundancy code generated by the error correction circuitry;
a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code from the first redundancy code storage; and
a copy address storage to store an address corresponding to data copied from the first redundancy code storage to the second redundancy code storage when the processor core restarts operation,
wherein the error correction circuitry comprises:
state determination circuitry to determine a state of whether a processor core is operating or stopped based on the address stored in the copy address storage; and
a redundancy code flow controller to control reading and writing of the redundancy code in the first redundancy code storage and the second redundancy code storage based on the state determined by the state determination circuitry,
wherein the second redundancy code storage is used for storing and reading the redundancy code during an operation of the processor core, and
wherein the redundancy code flow controller controls copying of the redundancy code from the second redundancy code storage into the first redundancy code storage when the processor core stops the operation, and then controls copying of the redundancy code from the first redundancy code storage into the second redundancy code storage when the processor core restarts the operation.
2. The cache memory according to claim 1 ,
wherein the cache memory circuitry stores tag information for access to the data, and
wherein the first redundancy code storage and the second redundancy code storage are capable of storing a redundancy code of the data stored in the cache memory circuitry and a redundancy code of the tag information corresponding to the data stored in the cache memory circuitry.
3. The cache memory according to claim 1 , wherein the second redundancy code storage stores information as to whether or not the redundancy code stored in the first redundancy code storage is stored into the second redundancy code storage when the processor core restarts the operation.
4. The cache memory according to claim 1 , further comprising a first storage which stores the redundancy code generated by the error correction circuitry before the redundancy code is stored in the first redundancy code storage,
wherein the first redundancy code storage stores the redundancy code when the first storage does not perform a write operation, and
wherein the first redundancy code storage stores the redundancy code which is present in the first storage and is not yet stored in the first redundancy code storage when the processor core stops the operation.
5. The cache memory according to claim 1 , wherein the nonvolatile memory cell of the cache memory circuitry is a magnetoresistive RAM (MRAM) cell.
6. A processor system comprising:
a processor core; and
a cache memory,
wherein the cache memory comprises:
cache memory circuitry comprising a nonvolatile memory cell storing a data;
error correction circuitry to generate a redundancy code of the data in the cache memory circuitry;
a first redundancy code storage comprising a nonvolatile memory cell capable of storing the redundancy code generated by the error correction circuitry;
a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code from the first redundancy code storage;
a copy address storage to store an address corresponding to data copied from the first redundancy code storage to the second redundancy code storage when the processor core restarts operation,
wherein the error correction circuitry comprises:
state determination circuitry to determine a state of whether the processor core is operating or stopped based on the address stored in the copy address storage; and
a redundancy code flow controller to control reading and writing of the redundancy code in the first redundancy code storage and the second redundancy code storage based on the state determined by the state determination circuitry,
wherein the second redundancy code storage is used for storing and reading the redundancy code during an operation of the processor core, and
wherein the redundancy code flow controller stores controls copying of the redundancy code from the second redundancy code storage into the first redundancy code storage when the processor core stops the operation, and then controls copying of the redundancy code from the first redundancy code storage into the second redundancy code storage when the processor core restarts the operation.
7. The processor system according to claim 6 ,
wherein the cache memory circuitry stores tag information necessary for access to the data in addition to the data, and
wherein the first redundancy code storage and the second redundancy code storage are capable of storing a redundancy code of the data stored in the cache memory circuitry and a redundancy code of the tag information corresponding to the data stored in the cache memory circuitry.
8. The processor system according to claim 7 , further comprising a first storage which stores the redundancy code generated by the error correction circuitry before the redundancy code is stored in the first redundancy code storage,
wherein the first redundancy code storage stores the redundancy code when the first storage does not perform a write operation, and
wherein the redundancy code flow controller performs control of storing the redundancy code which is present in the first storage and is not yet stored in first redundancy code storage when the processor core stops the operation.
9. The processor system according to claim 6 , further comprising:
a first semiconductor chip on which the cache memory circuitry and the first redundancy code storage are provided; and
a second semiconductor chip on which the processor core and the second redundancy code storage are provided, the second semiconductor chip being stacked with the first semiconductor chip.
10. The processor system according to claim 6 , wherein the nonvolatile memory cell of the cache memory circuitry is a magnetoresistive RAM (MRAM) cell.