Semiconductor device and fabricating the same
The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.
1. A device comprising:
a substrate having a first region and a second region;
a first gate region and a first source/drain feature separated from a second source/drain feature by the first gate region in the first region; and
a second gate region and a third source/drain feature separated from a fourth source/drain feature by the second gate region in the second region, and
wherein the first gate region includes a plurality of first nanowire sets having a first semiconductor material, the first nanowire sets extending between the first source/drain feature and the second source/drain feature,
wherein the second gate region includes a plurality of second nanowire sets having a second semiconductor material, the second nanowire sets extending between the third source/drain feature and the fourth source/drain feature,
wherein an anti-punch through feature is disposed in the substrate under one of the first nanowire sets from the plurality of first nanowire sets and a sidewall spacer is disposed between a portion of the first gate region and the first source/drain feature such that the sidewall spacer extends along a sidewall of the anti-punch through feature.
2. The device of claim 1 , wherein another anti-punch through feature is disposed in the substrate under one of the second nanowire sets from the plurality of second nanowire sets and another sidewall spacer is disposed between a portion of the second gate region and the third source/drain feature such that the another sidewall spacer extends along a sidewall of the another anti-punch through feature.
3. The device of claim 2 , wherein the anti-punch through feature is implanted with p-type dopants, and
wherein the another anti-punch through feature is implanted with n-type dopants.
4. The device of claim 1 , further comprising another sidewall spacer disposed between a portion of the first gate region and the second source/drain feature such that the sidewall spacer extends along another sidewall of the anti-punch through feature.
5. The device of claim 4 , wherein the one of the first nanowire sets extend from the sidewall spacer to the another sidewall spacer.
6. The device of claim 1 , wherein the first gate region further includes a high-k dielectric layer wrapping around one of the nanowires from the plurality of first nanowire sets and a metal gate electrode wrapping around the high-k dielectric layer.
7. The device of claim 1 , wherein the first region is one of an NMOS region and a PMOS region and the second region is the other of the NMOS region and the PMOS region.
8. The device of claim 1 , wherein the first source/drain feature and the sidewall spacer extend below the anti-punch through feature.
9. The device of claim 8 , wherein the first source/drain feature and the sidewall spacer extend below a topmost surface of the substrate.
10. The device of claim 8 , wherein a bottommost surface of the source drain/feature is substantially coplanar with a bottommost surface of the sidewall spacer.
11. The device of claim 1 , wherein:
the anti-punch through feature is a first anti-punch through feature;
the device further comprises a second anti-punch through feature under the plurality of first nanowire sets and an isolation feature disposed between the first anti-punch through feature and the second anti-punch through feature; and
a bottommost surface of the isolation feature is substantially coplanar with a bottommost surface of the first anti-punch through feature and a bottommost surface of the second anti-punch through feature.
12. A device comprising:
a substrate having a sidewall;
a first source/drain feature disposed on the substrate;
a second source/drain feature disposed on the substrate;
a first gate region disposed on the substrate, wherein:
the first source/drain feature is separated from the second source/drain feature by the first gate region, and
the first gate region includes a first nanowire formed of a first semiconductor material extending between the first source/drain feature and the second source/drain feature;
and
a first sidewall spacer disposed in a portion of an area between the first gate region and the first source/drain feature and extending along the sidewall of the substrate.
13. The device of claim 12 , further comprising:
a first anti-punch through feature disposed in the substrate under the first nanowire such that the first sidewall spacer extends between the first anti-punch through feature and the first source/drain feature;
a second nanowire formed of the first semiconductor material extending between the first source/drain feature and the second source/drain feature;
a second anti-punch through feature disposed in the substrate under the second nanowire; and
a second sidewall spacer disposed in a portion of an area between the first gate region and the second/source drain feature and extending along a sidewall of the second anti-punch through feature.
14. The device of claim 13 , further comprising a gate dielectric layer extending from the first anti-punch through feature to the second anti-punch through feature.
15. The device of claim 13 , further comprising a first isolation feature disposed in the substrate and extending from the first anti-punch through feature to the second anti-punch through feature.
16. The device of claim 15 , further comprising a second isolation feature disposed in the substrate adjacent the first anti-punch through feature, wherein the first isolation feature extends in the substrate to a first depth and the second isolation feature extends into the substrate to a second depth that is greater than the first depth.
17. The device of claim 12 , further comprising:
a first anti-punch through feature disposed in the substrate under the first nanowire such that the first sidewall spacer extends between the anti-punch through feature and the first source/drain feature;
a third source/drain feature;
a fourth source/drain feature;
a second gate region, wherein:
the third source/drain feature is separated from the fourth source/drain feature by the second gate region, and
the second gate region includes a second nanowire formed of a second semiconductor material extending between the third source/drain feature and the fourth source/drain feature;
a second anti-punch through feature disposed in the substrate under the second nanowire and having a sidewall; and
a second sidewall spacer extending along the sidewall of the second anti-punch through feature between the second anti-punch through feature and the third source/drain feature.
18. The device of claim 17 , wherein the first semiconductor material is different than the second semiconductor material.
19. A device comprising:
a substrate;
a first source/drain feature disposed on the substrate;
a second source/drain feature disposed on the substrate;
a first nanowire extending from the first source/drain feature to the second source/drain feature;
a first gate dielectric layer wrapping around the first nanowire;
a first metal gate electrode wrapping around the first gate dielectric layer
a third source/drain feature disposed on the substrate;
a fourth source/drain feature disposed on the substrate;
a second nanowire extending from the third source/drain feature to the fourth source/drain feature;
a second gate dielectric layer wrapping around the second nanowire;
a second metal gate electrode wrapping around the second gate dielectric layer;
a first anti-punch through feature disposed in the substrate under the first nanowire; and
a first sidewall spacer extending along a sidewall of the first source/drain feature and along a sidewall of the first anti-punch through feature.
20. The device of claim 19 , further comprising a second anti-punch through feature disposed in the substrate under the second nanowire;
a second sidewall spacer extending along a sidewall of the third source/drain feature and along a sidewall of the second anti-punch through feature, and
wherein one of the first anti-punch through feature includes a first dopant type and the second anti-punch through feature includes a second dopant type that is opposite the first dopant type.